( ESNUG 387 Item 8 ) --------------------------------------------- [01/23/02]
From: "Gregg Lahti" <gregg.lahti@corrent.com>
Subject: How Do I Eliminate Extraneous DC Clock-Gating Hierarchy/Wrappers?
Hi John,
We're using the clock gating and scan insertion features in DC with a custom
clock gating cell. I've specified the clock_gating_style as a sequential
latch with control_point set to before and some appropriate bitwith and
max_fanout settings. Works fine through synthesis, but the output result
from DC adds a boatload of unique SNPS_CLOCK_GATE* wrappers around the clock
gating cell for all instances where the clock gating cell would be added:
module SNPS_CLOCK_GATE_HIGH_hdwb_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
GCKAD4 latch ( .TE(TE), .EN(EN), .CLK(CLK), .ENCLK(ENCLK) );
endmodule
Power Compiler adds this hierarchy at elaboration to attach a batch of
attributes required to map the clock gating cells, presumably for clock
gating and scan insertion. However, when going through the layout flow,
all of these modules represent an extra layer of hierarchy that needs to
get processed. Is there a way eliminate this extra layer of hierarchy and
still preserve the clock gating and scan attributes? It seems to me that
DC should just instance the cell and attach the attributes to the instance.
Removing this layer of hierarchy would really cut down the amount of
instances that need to get processed further down the layout methodology
path.
- Gregg Lahti
Corrent Corp. Tempe, AZ
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