( ESNUG 387 Item 1 ) --------------------------------------------- [01/23/02]
Subject: ( ESNUG 386 #10 ) Another Customer Pleads For C-Level's Technology
> C-Level Design had an incredible tool which allowed you to write your HDL
> in ANSI-C or C++. Their programming style guide showed you how to
> transform sequential C into something that could emulate the parallel
> operation of hardware. The key was that you could write the C-HDL at a
> low level (identical to Verilog or VHDL), but C simulation speeds were
> 3 orders of magnitude faster on large simulations. This C-HDL design
> could then be automatically translated to synthesizable Verilog - which
> synthesized to remarkably fast logic using Synopsys Design Compiler. ...
>
> If Synopsys takes this C technology and creates the next generation HDL
> that is capable of simulating at these remarkable speeds, I will be
> very happy.
>
> - Dan Joyce
> Compaq Austin, TX
From: "Doug Blettner" <dblettner@yottanetworks.com>
Hi John,
I just read Dan's ESNUG post and think it's right on. Thank Dan, for
taking the time and effort to post it. I hope it clears up some of those
misconceptions in the engineering community about C-Level's tools. I, too,
thought it was great technology. We didn't get to complete a project with
it, but we did buy it and were starting to use it on some projects. (This
was at another company, not Yotta.) My engineers found the learning curve
to be mild, liked using the tool, and got very good performance improvement.
(The projects didn't complete because of business reasons.)
When I heard about the Synopsys purchase I had the same reaction as Dan. I
hope the technology continues, but I'm afraid it will suffer the same fate
as MOTIVE, which we owned and were using successfully until Synopsys bought
and killed it in favor of PrimeTime.
Do you know if it's still possible to buy the C Level tools now?
- Doug Blettner
Yotta Networks, Inc. Plano, TX
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