( ESNUG 386 Item 10 ) -------------------------------------------- [01/16/02]
From: "Dan Joyce" <dan.joyce@compaq.com>
Subject: User Hopes That Synopsys Doesn't Kill C-Level's EDA C Technologies
Hi, John,
It was announced Nov. 12th that C-Level Design was acquired by Synopsys.
C-Level Design had an incredible tool which allowed you to write your HDL in
ANSI-C or C++. Their programming style guide showed you how to transform
sequential C into something that could emulate the parallel operation of
hardware. The key was that you could write the C-HDL at a low level
(identical to Verilog or VHDL), but C simulation speeds were 3 orders of
magnitude faster on large simulations. This C-HDL design could then be
automatically translated to synthesizable Verilog - which synthesized to
remarkably fast logic using Synopsys Design Compiler.
In ESNUG, I keep reading "Now that the Verilog/VHDL wars are over, you
idiots are trying to start a C++/Verilog war!".
I don't view it that way. C++ is not an alternative to Verilog. It is an
*addition* to Verilog - yes with all the baggage of learning two languages.
But for people who need to simulate such large designs and run great
numbers of cycles (random testing approaches), C was worth it. With the
C-Level solution, Verilog was still an integral part of the process. A
portion of the simulation was always required at the Verilog level. When
will anyone ever sign off on an ASIC without a Verilog gate level simulation
for at least a subset of the regression suite? - Not in this decade.
The supposed downsides to this were:
1) C simulations are only cycle accurate. This isn't a big a deal because:
- Most Verilog simulations today using event driven simulators have
all clocks running at some multiple of a single clock anyway.
Asynchronous logic is verified using other means (usually code
inspection).
- Don't forget you are translating to Verilog. You can do all the
event driven simulation you want with the Verilog translation of
the logic. C or C++ just gives the opportunity to run the majority
of the logic verification at much higher speeds when all you need
is cycle accuracy.
2) Lack of C tools. Good waveform debugging, code coverage, linting,
assertion, and test-language tools are still missing from the C/C++
space.
- These were being created and would not have taken long to complete.
- Actually C++ is a much better test language than Verilog to start
with. Vera was created to give C++ capabilities to Verilog users.
3) Verilog code as legacy or cores. Simulation speeds of 3 orders of
magnitude faster could not be achieved if ANY Verilog or VHDL was running
in the simulation. The slower code, could easily be tied into the
simulation with PLI, but no matter how small the code was, it would grind
the simulation speed back to nearly Verilog speeds. Workarounds:
- C-Level was working on Verilog uplifting to create a faster cycle
accurate C model of most Verilog code.
- Include only C++ for the C++ simulation environment. Different
simulation environments to verify the parts that cannot be in C++.
According to the aquisition Press Release, Synopsys plans to integrate this
technology into their VCS tool. It will be interesting to see how they
manage to do this. Here are their options:
1) Market C-Level's tool mostly as-is. This would include the programming
style guide, uplifter from legacy Verilog to cycle accurate C++, and C++
to synthesizable Verilog translator.
- They have already said they will not do this, instead leveraging the
technology into their existing tools.
2) Create a new cycle accurate Verilog simulator. This would come no where
close to the simulation speeds of C-Level's ANSI-C solution but could be
faster than present VCS.
- They are already doing this and nothing from C-Level will help in
this effort.
3) Create a second simulation kernel for SystemC which runs cycle accurate
and much faster than the present one.
- This would still have to have a kernel and would not achieve the
simulation speeds that C-Level was able to achieve, but could be
much faster than the present event driven SystemC or even a cycle
accurate VCS.
- C-Level allowed users to program in Open source ANSI-C++. This gave
quite a high level of flexibility. Synopsys will probably not
change SystemC to run as Open Source C++.
4) Swallow C-Level just to keep it from competing w/ their existing tools.
If Synopsys takes this C technology and creates the next generation HDL that
is capable of simulating at these remarkable speeds, I will be very happy.
Despite the pain of this new technology and the lack of tools and expertise,
the advantages were more than worthwhile for certain projects. As chip
sizes increase faster than Verilog simulators speed up, the need for this
type of C-HDL solution will only become more pressing.
If Synopsys does not use this C technology, or takes an approach that loses
most of the speed advantage, someone else eventually will. There are enough
customers who need to simulate very large designs and will be willing
finance this type of tool. It has already been done and technically proven.
- Dan Joyce
Compaq Austin, TX
|
|
