( ESNUG 386 Item 9 ) --------------------------------------------- [01/16/02]
Subject: ( ESNUG 385 #13 ) Mixed Voltage Libs Mess Up DC/Apollo/PrimeTime
> I just received word from a Synopsys AC that if I have a PAD and a CORE
> library that have two different operating voltages, then I end up with
> significant problems in Apollo, Design Compiler and PrimeTime. ...
>
> Design Compiler (presently, I know the new library format is coming) can
> only handle ONE operating condition. Not one per library. Can someone
> shed some light on this problem?
>
> - Wayne Miller
> Standard Microsystems Corporation
From: "Keith Buckingham" <keith@nvidia.com>
Hi, John,
It has been my experience that we have to specify the intended *core*
operating conditions in our pad libraries, although we recognize that this
is not strictly speaking the conditions that the pad transistors are seeing.
eg.
/* These are the conditions that the library was extracted at
* but the library will be used at the second set of conditions below
* and we do not want the library to scale, so we declare those
* conditions as being the ones for the library
nom_process : 1;
nom_temperature : 125;
nom_voltage : 0.95;
*/
nom_process : 1;
nom_temperature : 125;
nom_voltage : 1.08;
This is more of a maintenance overhead if you want to perform cross corner
timing analysis (min-voltage core + max-voltage IO), but if you only do
min-min and max-max, then it just becomes an understood difference to the
nominal operating conditions declaration.
- Keith Buckingham
NVIDIA
---- ---- ---- ---- ---- ---- ----
From: "Robert Wiegand" <RWiegand@NxtWaveComm.com>
Hi John,
Wayne might want to try the following SolvIt article: Synthesis-654.html.
It describes two solutions, one modifying the k_volt parameters in the pad
library, and the other modifying the nominal voltage in the pad library.
Another article, Synthesis-838.html, suggests changing the k_volt parameters
to zero to prevent any scaling. Both, of course, require access to the .lib
files as well as a Library Compiler license if you need to create new .db
files. So far, the few people I have talked to about this have just decided
to live with the slower pad timings that result from not doing these
modifications. I haven't tried these workarounds myself yet, so I can't
confirm if they work (I was able to live with slower pad timing).
While we're talking about scaling, what about temperature? Let's say I have
a cell library with best case defined at -40 C, but the pad library has it's
best case characterized at 0 C. If I use the core operating conditions,
will the pad library k factors scale the pads and speed them up? Is there
some other way to match the pad temperature to the core temperature?
- Bob Wiegand
NxtWave Communications Langhorne, PA
|
|
