( ESNUG 385 Item 13 ) -------------------------------------------- [12/19/01]
From: "Wayne Miller" <Wayne.A.Miller@smsc.com>
Subject: Help! These Mixed Voltage Libs Are A DC/Apollo/PrimeTime Nightmare!
Hi John,
I just received word from a Synopsys AC that if I have a PAD and a CORE
library that have two different operating voltages, then I end up with
significant problems in Apollo, Design Compiler and PrimeTime.
Let me explain.
For a 0.25u core library, my Synopsys libraries have the following
definitions:
best case: 2.75 V
typical: 2.5 V
worst case: 2.25 V
My 3.3V PAD library has the following definitions:
best case: 3.6 V
typical: 3.3 V
worst: 3.0 V
Now, if I specify my operating condition as typical (from the core library)
for timing analysis, then the timing engine (Apollo, Design Compiler, or
PrimeTime) does the following. For core cells:
core typical voltage = 2.5 V
operating voltage = 2.5 V
scaled timing = timing + (2.5 - 2.5) * delta = Typical core timing
(as expected)
For PAD cells:
PAD typical voltage = 3.3 V
operating voltage = 2.5 V
scaled timing = timing + (3.3 - 2.5) * delta = Some other timing, (not what
I expected nor want)
This can't be true! Can it? What am I missing?
Design Compiler (presently, I know the new library format is coming) can only
handle ONE operating condition. Not one per library. Can someone shed some
light on this problem?
- Wayne Miller
Standard Microsystems Corporation
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