( ESNUG 383 Item 2 ) -------------------------------------------- [11/28/01]

From: "Ofer Paperni" <ofer.paperni@motorola.com>
Subject: Verilog Doesn't Like The Case Of My PhysOpt 'write_script' Output

Hi John,

My design has signal names with UPPER and lower case.  When I'm doing
'write_script' in PhysOpt, it writes all of the signals in lower case.
Verilog doesn't like this.  How can I fix PhysOpt so the names in the
write_script will be liked in Verilog?

    - Ofer Paperni
      Motorola
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