( ESNUG 381 Item 10 ) ------------------------------------------- [11/08/01]
From: Daniel Szoke <Daniel.Szoke@nsc.com>
Subject: Seeking User Experiences With New VHDL To Verilog Transation Tools
Hi, John,
We need to do a design involving mixed VHDL & Verilog. Our first preference
would be to translate the VHDL parts to Verilog (our standard language) for
maintainability. I would like to question your readers regarding their
experience with translation tools. (ESNUG dealt with this issue back in
1995 but I expect there have been some advances since then.) Especially:
1. What VHDL constructs are/were translated
2. Quality (readability) of the translated Verilog
3. Compare synthesis of: VHDL -> gates VS. VHDL -> Verilog -> gates
4. Compare sim of: mixed VHDL-Verilog VS. translated Verilog-Verilog
Thanks to all.
- Daniel Szoke
National Semiconductor Israel
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