( ESNUG 379 Item 7 ) -------------------------------------------- [10/11/01]
Subject: ( ESNUG 378 #5 ) Cadence CTGEN vs. Silicon Perspectives Benchmark
> Cadence CTGEN's results: 466 ps skew, max trans of 490 ps, met the
> insertion delay, took around 6 hours, 3498 buffers used.
>
> Silicon Perspective FE clock tree results: 162 ps skew, max trans of
> 480 ps, met the insertion delay, took 7 minutes, 1820 buffers used.
From: "Donepudi Narasayya" <donepudi.narasayya@st.com>
Hello John,
I think that the slew & skew figures given in this benchmark are generated
by the clocktree generation tools right after clock tree generation. It
would be interesting to know the values of skew & slew after signal routing.
CTGen has an option of reporting post-route skew & slew if you provide it
with an RSPF. This can help us know how good is the correlation between
pre-route and post-route values (especially of the skew.)
In general, skew analysis done with a neutral STA tool like PrimeTime would
be more acceptable. This is because, CTGEN and First Encounter may have
different timing engines.
If the person who did the benchmark can do such post-route analysis also,
the benchmark would then be more realistic.
- Donepudi Narasayya
STMicroelectronics
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From: [ The Lone Ranger ]
John, keep me anon.
I have some questions. These results look very impressive, but please give
us more and meaningful details! For example:
- Were his timing numbers pre-route, post-route, or post-extraction?
- Was WRoute used for routing?
- What was the utilization of the design?
- What extraction tool was used?
- What were the clock frequencies?
- Where were the CT buffers legalized?
- Did the pre-route and post-extraction timing numbers correlation?
I am not challenging his results, but numbers w/o this context are about as
meaningful as a timing report out of DC with WLMs in a 0.10 library!
If these numbers were pre-route, then they are might not be as exciting. A
guy could write his CTS tool in Perl and do better than SPC and CTGen (as
long as he used his own timing engine, was optimistic about interconnect
delay, and slapped the buffers any which where!)
- [ The Lone Ranger ]
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From: "Jim Jok" <jok@erols.com>
John,
Did this post indicate if the user's results were obtained with post-routed
SDF? Or were they obtained from the preliminary report which comes from
clock tree insertion tools. Normally the initial report is based on steiner
routing or some other ball-park algorithm for routing estimates. To be
fair, the post-routed SDF should be used.
We have noticed that CTGEN is using 'extra' buffers, also. The tool seems to
fair well with small die, but on the larger dies the tool is behaving as
this user pointed out. As in most production environments, time for doing
what-if and detailed analysis is hard to come by. Thus the solution is the
main goal. The vendor needs to do some serious looking at these issues or
lose out to the competition.
The combination of large die and high-speed requirement is a hurdle that
might be new to the existing CTGEN algorithm and the algorithm needs to be
re-visited and possibly refined. Also, did Silicon Perspective use the same
array LEF as the CTGEN tool or were parasitics obtained from some other
step? i.e. 8 minutes vs. time for some other step to get parasitics plus 8
minutes?
Maybe this user's benchmark could be thrown to the CTGEN developers to
determine if they can drive the tool to meet the required performance.
I would like to see Cadence address the clock tree issue since if one is
using a Cadence flow, life is much simpler if you can stick with CTGEN.
- Jim Jok
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From: "Eric Meyer" <eric.meyer@audiologic.cirrus.com>
John,
We've seen some "interesting" CT-Gen behavior related to not having accurate
caps in the .LEF file (e.g., too many buffers, optimistic/pessimistic skew,
and optimistic/pessimistic insertion delay.)
I'd be interested in other's experience with Silicon Perspectives FE and
whether or not they got back good Silicon.
- Eric Meyer
Cirrus
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