( ESNUG 378 Item 10 ) ------------------------------------------- [10/03/01]
From: "Louis Villarosa" <Louis.Villarosa@honeywell.com>
Subject: Must I Use An Analog Simulator Along With PrimeTime For PCI Specs?
Hello, John,
The Local PCI Bus Specification specifies the maximum clock-to-output delay.
However, for the 3.3 v signal environment, the load capacitance is not
given. Instead the specification defines V/I curves for the output driver
and states that the output current must exceed a specified value with the
maximum clock-to-output time. The reason for this is that outputs drive a
backplane trace. Therefore lumped load models don't apply. It does not
appear that it is possible to strictly use PrimeTime to calculate the delay
or to constrain the synthesis to meet the PCI output delay requirement.
One approach is to constrain the delay using the set output delay and use
some arbitrary load capacitance. Then using PrimeTime to generate a
timing report for the clock-to-output paths. From the the timing report
determine the delay up to the input of the PCI output buffer. To determine
the delay associated with the buffer use an analog simulator tool like
Interconnectix and IBIS models simulate the driver and the backplane. Add
this delay to the internal delay from the PrimeTime report to get the
total delay.
Is this good appoach or is there a way to do this strictly using PrimeTime?
- Lou Villarosa, Jr.
Honeywell Space Systems Clearwater, FL
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