( ESNUG 378 Item 2 ) -------------------------------------------- [10/03/01]
Subject: ( ESNUG 377 #2 ) Turning Off The Secret "Consume Licenses" Switch
> Synopsys seems to grab a VHDL-Compiler license for no apparent reason
> during compile. I am running a Verilog-only synthesis with no DesignWare
> (or other VHDL originated components):
>
> read -f verilog srom_cntrl.v
> ...
> remove_license HDL-Compiler
> 1
> list -licenses
> Design-Compiler
> LUCENT-HL160C
> LUCENT-LV160C
> 1
> compile -map_effort medium
> ...
>
> Optimization Complete
> ---------------------
> Transferring design 'srom_cntrl' to database 'srom_cntrl.db'
> Current design is 'srom_cntrl'.
>
> 1
> list -licenses
> Design-Compiler
> LUCENT-HL160C
> LUCENT-LV160C
> VHDL-Compiler <<<<<*** Where did this come from?
> 1
>
> Of course, I'm sure that Synopsys would prefer that we buy a copy of
> VHDL-Compiler and HDL-Compiler for each copy of Design-Compiler that we
> have. This would certainly solve the problem... But, as you know John,
> I am a Verilog bigot, so the problem is even worse. If anyone checks
> license usage, people will think I'm doing VHDL synthesis runs and start
> making fun of me.
>
> - Romas Rudis
> Intrinsix
From: "Tom Cruz" <tomcruz@us.ibm.com>
Hi, John,
Has Romas tried setting the Synopsys variable:
hdl_prefered_license = verilog
You can do a list -variables all to see what it's currently set to. I think
the default is vhdl.
- Tom Cruz
IBM
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