( ESNUG 377 Item 13 ) ------------------------------------------- [09/19/01]
From: Robert Hindle <Robert.Hindle@st.com>
Subject: Help! How Can I Simulate 12.5 M Gate Designs In Verilog with SDF?
Hi John,
As part of the tapeout checklist for our large designs, we like to run a
subset of chip level tests using fully annotated gate-level simulations in
order to verify interconnect timing, false/multicycle paths and as a general
sanity check of our flow. This has been OK until recently, when we started
hitting the limits of our tried-and-tested simulation tools. I've tried a
few different simulators on Solaris, but anything running at 32-bits will
not cope. We hit the 4 Gb footprint limit. I'm now looking to using 64-bit
simulators as a solution to our problem, Modelsim being the only one I've
tried so far. Is this the only 64-bit simulator available at the moment?
I wanted to garner opinon from any of your readers who have experienced
similar problems, what tools they've found to provide good performance/price
(or not, as the case may be) and what problems they may have faced porting
to 64-bits (eg. PLI routines, memory usage etc.)
I'm running on Solaris 2.7/2.8 machines with up to 12Gb of total available
memory.
- Robert Hindle
STMicroelectronics
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