( ESNUG 377 Item 10 ) ------------------------------------------- [09/19/01]
Subject: ( ESNUG 375 #1 ) Extract A Hierarchy From A Flat Gate Netlist
> When we do minor (typically metal-only) re-spins of our devices. We make
> our changes by hand at the gate level. We've gotten good at specifying
> the gate changes, but have run into a roadblock in verifying them. In the
> old days, our gate level netlists preserved hierarchy, and so it was easy
> to extract the module containing the fix and either use it to replace the
> RTL block in simulation, or (more recently) re-synth the RTL and
> Formality-check the synth'd gates to the hand-fixed gates. However,
> things like clock-tree-insertion and scan-reordering are now causing our
> gate-level netlists to be totally flat. Extracting a block of gates
> that's bristle-equivalent to an RTL block has become a non-trivial task.
> I was wondering if anyone out there had licked this problem?
>
> - Jeff Winston
> Mindspeed Technologies
From: "Doug Baumann" <doug.baumann@zeevo.com>
Hi John,
We've run into similar problems. Our designs contain complex modules which
formal tools have difficulty proving against a flattened netlist. What
we've chosen is a 2-part verification which adds a little overhead but
provides a robust solution (so far). The method is to keep a hierarchical
gate-level netlist around in addition to the post-layout flat netlist. The
hierarchical netlist does not contain scan chains, clock trees, or other
messy, post-synthesis changes.
The first step is to replicate the ECO changes in the hierarchical gate-
level netlist, then formally verify the hierarchical netlist to the ECO'd
RTL. The second step is to replicate the changes in the flattened post-
layout netlist, then formally verify against the ECO'd hierarchical gate-
level netlist.
There is a little more work to maintain a golden hierarchical and post-
layout netlist, however it is well worth it when you can know for certain
that your ECO was implemented correctly.
-Doug Baumann
Zeevo
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