( ESNUG 377 Item 4 ) -------------------------------------------- [09/19/01]
From: "Tommy Zounes" <tommy.zounes@st.com>
Subject: Here's How We Used PhysOpt For CTGEN Clock Buffer Legalization
Hi John,
Recently, a colleague of mine asked me about a design's cell placement after
CTGEN inserts clk buffering. I never thought about this before. I just
assumed CTGEN would slightly nudge the cells over to place the new clk
buffers. To check this, I wrote a small script that compared the initial
cell placement (done by PhysOpt) to the final CTGEN output. The design used
is 0.08 mm2, has 4,900 instances, utilization is about 92%, and uses 0.12
technology. About 80 buffers were added by CTGEN. The results revealed 140
cells moved from its original location by between 12um and 25um. About
2,500 other cells were moved by less than 12 um.
This may not seem too bad, but for a 0.4 um pitch routing technology, 62
grid difference is beginning to look quite high.
I then decided to try PhysOpt to do the legalization of the cells. CTGEN
provides a DEF output file without the cells being legalized in the
<rundir>/db/qp_in.def. To be able to use PhysOpt, a Verilog netlist with
the clock tree inserted is needed. I've written SKILL routines that can
convert a DEF-in layout to Verilog. It would be nice to have a script that
can create a Verilog netlist directly from DEF!
Anyway, in the DEF file, the new clk buffers need to have their placement
set to "FIXED", otherwise PhysOpt may move these a little. I also thought
about FIXing the register placements. But in this case I did not since I
was unsure what PhysOpt would do if a clk buffer overlapped a register cell.
Also in the DEF, some clk syntax added by CTGEN needs to be removed because
Synopsys' def2pdef will give a syntax error. So when running psyn_shell, I
just load the new Verilog gate netlist and the new DEF, and I just run the
'legalize_placement' command.
The new placement results revealed no cells were moved more than 12 um.
2,800 cells were moved by less than 12um.
It would be interesting to see results from other designs.
- Tommy Zounes
ST Microelectronics
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