( ESNUG 375 Item 1 ) -------------------------------------------- [06/28/01]
From: Jeff Winston <jeff.winston@mindspeed.com>
Subject: How Can I Extract A Hierarchical Module From A Flat Gate Netlist?
Hi, John,
When we do minor (typically metal-only) re-spins of our devices. We make
our changes by hand at the gate level. We've gotten good at specifying
the gate changes, but have run into a roadblock in verifying them. In the
old days, our gate level netlists preserved hierarchy, and so it was easy
to extract the module containing the fix and either use it to replace the
RTL block in simulation, or (more recently) re-synth the RTL and
Formality-check the synth'd gates to the hand-fixed gates. However, things
like clock-tree-insertion and scan-reordering are now causing our gate-level
netlists to be totally flat. Extracting a block of gates that's
bristle-equivalent to an RTL block has become a non-trivial task. I was
wondering if anyone out there had licked this problem?
- Jeff Winston
Mindspeed Technologies
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