( ESNUG 374 Item 4 ) -------------------------------------------- [06/14/01]
Subject: ( ESNUG 373 #11 ) Cadence SE-SI Vs. Simplex Electromigration
> With our move to technologies below 0.18 and clock speeds in the upwards
> of 300+ Mhz, we are finding the need to run electromigration analysis on
> our signal nets. Unfortunately, most EM analysis tools available today
> are for power nets. Have you heard anything from the masses about this?
>
> So far, I've only uncovered ElectronStorm by Simplex as the only tool
> currently in the market that does EM analysis on signal nets. Am I
> missing something here? There's got to be more out there than this.
> Avanti has something in the works for this, but it won't be available
> until Q1/Q2 of 2002. What about Synopsys, Cadence, Mentor Graphics? Any
> new startups? HELP!
>
> - Caesar M. Abedin
> Applied Micro Circuits Corp. Andover, MA
From: Lou Scheffer <lou@cadence.com>
Hi, John!
Cadence has such a signal wire EM tool, and has had one for quite some time.
The Cadence tool SE-SI (Silicon Ensemble - Signal Integrity) has handled
the signal line electromigration problem for several years. We call this
effect 'wire self heat', but it's the same effect. It's also sometime
called 'Joule heating'.
It works like this:
During placement, we estimate the wire load (quite accurately, it's from the
global route) and calculate the slew rate.
Then we need the maximum switching frequency of the net. We find this as
follows:
1) clocks we know (gating is ignored);
2) flops or latches are assumed to switch once/clock;
3) combinatorial logic is assumed to switch at the rate of the fastest
input.
or the user can tell us the max switching rate as a property.
Then, for each wire, we calculate the peak, RMS, and average current.
If any layers or vias have current limits in the LEF technology file (they
are a function of width and frequency, on both metal and vias) then we
compare the current to the limit.
You can get a report (see below) and decide on the fix yourself, or tell
the placer to fix it automatically. It does this by reducing the load by
changing the placement or inserting buffers.
Here is an example of the Qplace command file to generate the report:
inputFormat SiliconEnsemble
lefName example.lef
defName "ROUTED.def sbc.def"
ReportMode
inputGCFTimingLibraries "mpeg.tlf.gcf"
inputGCFConstraints "mpeg.constr.gcf"
timingMode TRUE
timingTruncateReport false
optSISelfHeatReportName POST.optSISelfHeatReport
Here is an example of the report. In this report positive numbers represent
violations; negative numbers represent margin.
# Self heat report created by ULTRA PLACER on Thu May 10 08:52:38 2001
SELF HEAT REPORT:
6 self heat violations out of 12097 nets
1. Self-heat violation histogram:
Violation (mA) #net
----------------------------------
-2.970 to -2.805 2
-2.805 to -2.640 0
-2.640 to -2.475 0
-2.475 to -2.310 1
-2.310 to -2.145 0
-2.145 to -1.980 0
-1.980 to -1.815 0
-1.815 to -1.650 1044
-1.650 to -1.485 32
-1.485 to -1.320 6
-1.320 to -1.155 0
-1.155 to -0.990 4
-0.990 to -0.825 0
-0.825 to -0.660 8220
-0.660 to -0.495 1840
-0.495 to -0.330 48
-0.330 to -0.165 887
-0.165 to -0.000 7
-0.000 to 0.165 6
0.165 to 0.330 0
2. Violation summary information
Net Total Trans Maximum Peak RMS Average Vio
name cap time freq current current current
(pF) (ns) (MHz) (mA) (mA) (mA)
usb_bus_out[4] 1.5078 0.3741 100.0 10.0756 2.7561 0.7539 0.0593
usb_bus_out[7] 1.4600 0.3741 100.0 9.7559 2.6686 0.7300 0.0354
usb_bus_out[5] 1.4333 0.3741 100.0 9.5775 2.6198 0.7166 0.0220
usb_bus_out[6] 1.4175 0.3741 100.0 9.4722 2.5910 0.7088 0.0142
usb_bus_out[3] 1.4044 0.3741 100.0 9.3844 2.5670 0.7022 0.0076
usb_bus_out[2] 1.3908 0.3741 100.0 9.2938 2.5422 0.6954 0.0008
usb_bus_out[1] 1.3792 0.3741 100.0 9.2161 2.5210 0.6896 -0.0050
[ lots of information on other nets deleted ]
3. Detailed violation information
Net Vio Layer Current Current Current
Name Name Type Value Limit
usb_bus_out[4] 0.0593 metal5 Avg 0.7539 0.6946
usb_bus_out[7] 0.0354 metal1 Avg 0.7300 0.6946
usb_bus_out[5] 0.0220 metal1 Avg 0.7166 0.6946
usb_bus_out[6] 0.0142 metal1 Avg 0.7088 0.6946
usb_bus_out[3] 0.0076 metal1 Avg 0.7022 0.6946
usb_bus_out[2] 0.0008 metal1 Avg 0.6954 0.6946
Note that the transition time reported here is a 0-100% time. This
is the 20-80 or 10-90 time extrapolated to 0-100% for the purpose of
current calculation. (In other words we are assuming each signal
transition is a saturated ramp).
Here is the relevant part of the LEF file:
LAYER contact
TYPE CUT ;
ACCURRENTDENSITY AVERAGE
FREQUENCY 1 5 20 50 80 110 140 170 200 230 260 290 320 350
380 410 440 470 500 ;
CUTAREA 1.3 ;
TABLEENTRIES
1.3 1.3813 1.4625 1.5438 1.625 1.7063 1.8 2.4 3 3.6 4.2
4.8 5.02 5.05 5.08 5.11 5.14 5.17 5.2 ;
SPACING .4 ;
END contact
LAYER metal1
TYPE ROUTING ;
ACCURRENTDENSITY AVERAGE
FREQUENCY 1 5 20 50 80 110 140 170 200 230 260 290 320 350 380
410 440 470 500 ;
WIDTH .6 ;
TABLEENTRIES
.748 .82925 .9105 .99175 1.073 1.2 1.8 2.4 3 3.6
4.2 4.8 5.02 5.05 5.08 5.11 5.14 5.17 5.2 ;
PITCH 1.04 ;
OFFSET .52 ;
WIDTH .6 ;
SPACING .32 ;
DIRECTION HORIZONTAL ;
RESISTANCE RPERSQ .53E-01 ;
CAPACITANCE CPERSQDIST .42E-04 ;
EDGECAPACITANCE .113E-03 ;
END metal1
I hope this helps your reader, John.
- Lou Scheffer
Cadence
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