( ESNUG 373 Item 6 ) -------------------------------------------- [06/07/01]
From: Rajendra Marulkar <Rajendra.Marulkar@InviscidNetworks.com>
Subject: Help! DC 99.10-6 Keeps Putting 2 Inverters In My Reset Paths!
Hello, John,
I am using DC 99.10-6. We are doing a million gate bottom up synthesis.
We are planning to use CTS both for the reset and clock networks. We put
following constraints on clk and reset:
set_drive 0 clock_grp
set_dont_touch_network clock_grp
set_drive 0 rst_l
set_dont_touch_network rst_l
But still DC puts 2 inverters in the reset path. Also there is no logic
between reset and flop in my design. Is there any issue with this version
of DC? (Interestingly it doesn't put any buffers/inverters on the clock
network path though its treated exactly like reset.)
- Rajendra Marulkar
Marconi Communications
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