( ESNUG 372 Item 10 ) ------------------------------------------- [05/31/01]
Subject: ( ESNUG 371 #11 ) Verplex Takes Minutes When Formality Takes Days
> Concerning run time performance we have seen a significant improvement in
> the recent year and some designs that used to be inconclusive now succeed.
> I'm talking about Formality 1999.10-FM1.0 vs. Formality 2000.05-FM2.0.
>
> I can give you some examples: one design was a RTL-to-Gate ~40K gates. It
> used to be inconclusive and now passes in ~2.5 hours. Another Gate2Gate
> design that was inconclusive now passes in 2 days. In this case I have
> just the container sizes around 20Mb (~500K gates). Often divisions send
> us containers in order not to make the code available. In effect this is
> a strange case for Gate2Gate but I think that designers took the first and
> the last version of gate netlists through a very complex flow.
>
> In these experiments we run Formality on the same machine: Sun Solaris
> 248MHz with 3.5 Gb memory.
>
> - Umberto Rossi
> STMicroelectronics Agrate Brianza, Italy
From: Tom David <tomd@cygnal.com>
Hi John,
With respect to the gentleman from ST's comments about Formality: here's
some live data from Verplex-LEC for a just completed design.
Design: about 44K gates with gated clocks and scan. (There were 2,917
comparison points.)
a) Gate-to-gate comparisons run in approx 7 mins on an Ultra II-300MHz
with 512MB.
b) Gate-to-RTL runs in approx 57 mins on an Ultra II-440MHz with 512MB.
The RTL and gates don't have exactly the same hierarchy either since
some blocks get flattened in our synthesis tool.
The above machines run Sun OS 5.6.
- Tom David
Cygnal
[ Editor's Note: Yes, Verplex has a rep for being much faster, but
since this isn't a case of running the same design on both Formality
and Verplex, it's somewhat misleading. Just my $.02. - John ]
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