( ESNUG 365 Item 9 ) --------------------------------------------- [02/15/01]
From: Matt Gavin <mtgavin@collins.rockwell.com>
Subject: Our Chip Express Clock Buffer Insertion Nightmares With DC 00.05
John,
We are having problems here at Rockwell with getting Design Compiler to
insert clock buffers in our designs. I was hoping some of your readers
could help. (Also, a big THANKS to those of you who have helped me with
questions in the past.) This is a somewhat long email; thanks in advance
to those who can follow it. FYI, we are currently using Synopsys 2000.05.
Our ASIC vendor (Chip Express) requires us to insert specific clock buffers
(as well as reset buffers) on our global clock and reset lines. We send the
vendor a pre-layout netlist; the vendor does place and route for us, so they
also do clock buffer tree synthesis. The buffer we insert is just a
placeholder for this buffer tree which Chip Express will insert.
Chip Express claims that Synopsys should be able to automatically insert the
(correctly sized) buffer for us. (Larger buffer sizes are used for larger
clock domains). However this has never worked for us. This is SUPPOSED to
work through two mechanisms: the 'max_capacitance' attribute, and the
'connection_class' attribute. Their library puts a connection_class
of CLOCK_NETWORK on all its flop clock inputs (and NO connection class on
its combinatorial cell inputs). The clock buffer output also has the
CLOCK_NETWORK connection class. So Design Compiler should (in theory) use
one of these clock buffers to fix connection_class violations on clock nets,
and the correct size will be chosen via the max_capacitance attributes on
the buffer output.
However, until recently, we had VERY little luck with getting this to work
on ANY clock. Recently we discovered that Synopsys 1999.05 and later
introduces the concept of "ideal nets" for all clocks by default (thus
exempting them from design rule fixing, which would keep the clock buffer
from being inserted.) The "set_auto_ideal_nets -none" compile command
overrides this ideal net inferrence. Using this command, we now get the
correct clock buffers on most clock nets, except clock nets which drive
non-flop clock inputs. As far as I can tell, Synopsys won't fix the
connection_class violation on clock nets that drive combinational
logic. (We don't get any clock buffer on these nets.) This is somewhat
understandable since inserting a clock buffer on such a net could itself
cause a violation (a pin of class CLOCK_NETWORK would be driving a pin
with no connection class at all). Still, it is disappointing to have a
clock net which drives 1000 flops and one "AND" gate, not get buffered
because it drives that one "AND" gate.
Does anyone have a remedy for this? We are at our wits' end here, and
we get VERY little support from Chip Express. I tried to override the
connection_class of the buffer outputs, to "CLOCK_NETWORK default", so the
buffers could be allowed to drive combinational logic, but that did
not work (did not get the buffers). Also, I could see Synopsys using these
buffers for non-clock purposes, if the above override actually worked.
Can I get Synopsys to insert a clock buffer on a net, if the *majority*
(but not all) of loads on that net, have that same connection_class
(CLOCK_NETWORK)?
Until we get this working, we have to hand-manipulate the netlist, either
in the source code, or in Synopsys. It would be much more preferable
to get Synopsys to do this automatically, especially since our designs
change frequently, and thus the buffer sizes do as well.
- Matt Gavin
Rockwell Collins
|
|
