( ESNUG 364 Item 3 ) --------------------------------------------- [02/01/01]
From: Tom Fairbairn <tomf@pdd.3com.com>
Subject: Memory Leak In "Automated Chip Synthesis" (ACS) Design Budgeter
Hi John,
Thanks as ever for ESNUG, but I've a question for the ESNUG folks. Has
anybody out there been using Automated Chip Synthesis (ACS)?
A long time ago (well, about the time 99.10 was released, actually), a man
from Synopsys came on site & told us all about the new synthesis environment
called ACS. ACS promised to eliminate the need for coming up with block
level constraint budgets. ACS promised to automate Design Budgeting. ACS
promised to look after our synthesis data for us. Pretty cool, we thought.
A few months ago we tried it on a real design. The ACS process ran out of
memory while generating the constraints for the second phase (pass 1)
compile. The Design Budgeter has a memory leak bug. Synopsys identified
a workaround, but that only works in 2000.5. There's no fix for 2000.11.
We're trying to get Synopsys to commit to a fix but it's hard going.
A question I asked Synopsys when we first found the problem was "has anyone
else used ACS?". They've been unable to come up with anything, so I was
wondering if anyone in the ESNUG community would like to share their
experiences? How they found its compile times, how well constraints were
met, impact on layout, gotchas and successful techniques etc.
- Tom Fairbairn
3Com Europe Ltd. Hemel Hempstead, UK.
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