( ESNUG 363 Item 14 ) -------------------------------------------- [01/25/01]
From: Jeff Winston <jeff.winston@conexant.com>
Subject: How To Insert Pass-Thru Signals In Hierarchical Physical Designs?
Hi John - hope all is well with you - got a question for ESNUG...
We are having our first experience with a large hierarchical design and are
trying to find the best way to handle global routing of signals that cross
blocks. We don't think the top-level routing ability of Apollo will do a
good enough job, and it also won't allow us to place buffers or flops where
we need them. We are thinking instead of embedding pass-thrus in different
blocks where needed to better facilitate the travel of these global signals
across the chip. As best we can tell, this will require adding the
pass-thru connectors (and flops if we use them) to the RTL of the blocks
containing the pass-thrus. However, we'd prefer not to mess directly with
the RTL that the designers are working with.
One idea we had was to put wrappers around the top-level RTL blocks and add
the pass-thru's (and flops if needed) to the wrappers. One could envision
developing a scripting environment to make this more less painful. However,
this will still change our hierarchy and require a fair amount of effort.
We were wondering if anyone else had come across this problem and how they
solved it.
- Jeff Winston
Conexant Systems
( ESNUG 363 Networking Section ) --------------------------------- [01/25/01]
San Diego, CA -- Intel Wireless Cellular Communications Group seeks 2 to 3
Jr/Sr ASIC Designers. No headhunters, please. "ihab.mansour@intel.com"
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