( ESNUG 363 Item 11 ) -------------------------------------------- [01/25/01]
From: Chris Simon <Chris.H.Simon@gd-is.com>
Subject: Our Cadence Hierarchical PBOPT Physical Chip Design Results Suck!
Hi, John,
I've never written to ESNUG before so I'm not quite sure if this is the
right place to ask this, but I'm desperate so here goes.
We're in the process of designing 3 standard cell ASICs and decided to use a
hierarchical approach for the physical design. The reasons for this are
many and varied, and I won't go into them here.
We use Cadence BuildGates (Ambit-RTL) to do synthesis, but also use Synopsys
in the flow to insert scan. All of this is done on a block level, where a
block can include anywhere from 4,000 to 50,000 instances as well as SRAMs
and register files. We then go to Cadence Logical Design Planner to
floorplan the block and place the cells using Qplace and QPOPT (their
replacement for PBOpt). We then ship the block off to a third party to
insert clocks, route the block, and extract parasitics. They use CTgen,
Silicon Ensemble, and HyperExtract. For the few blocks that we've completed
we've had very good luck achieving timing closure at the block level (even
though we aren't using Physical Compiler or PKS). This is one of the
reasons we chose the hierarchical approach.
As we get a good idea of the block sizes and shapes we floorplan the top
level, with around 15 blocks and the I/O cells. We ship the top level off
to the third party and they insert clocks at the top level. So far so good.
Now they try to fix the timing on the long nets between blocks using QPOPT,
and the results are horrendous. At this point we would have already
generated timing models for each of the blocks, and they are inputs to the
QPOPT runs. In many different attempts at top level timing optimization,
QPOPT has not been able to put in an appropriate number of buffers/repeaters
to achieve reasonable timing. I did some experimentation with long nets and
various numbers of buffers and found that I should be able to go 5 mm in
about 1.2 nS even with a less than optimum repeater scheme. QPOPT isn't
even getting close. When we talked to Cadence R&D about this they basically
said that QPOPT isn't intended to do this type of optimization.
So my question is, how are other people doing the timing optimization
(buffer and repeater insertion) at the top level for a hierarchical physical
flow? I've heard a lot of talk about hierarchical physical design being
necessary as designs get larger, and I've seen a couple of recent articles
on hierarchical design flows in ISD magazine, but they don't say much about
this topic. I tried to reach the authors of these articles to question
them, but had no luck. Would your readers have any answers here, or is
hierarchical flow still a pretty rare thing?
By the way, you're providing a great service to those of us out here trying
to get the damn tools to do what we need. Keep up the good work.
- Chris Simon
General Dynamics Information Systems Minneapolis, MN
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