( ESNUG 363 Item 4 ) --------------------------------------------- [01/25/01]
Subject: Newbies Struggle Trying To Control VCS from the PLI Interface
> I am attempting to drive VCS directly from another application using the
> PLI but I am having trouble actually getting the simulator to run for a
> specified length of time, e.g. a clock cycle. I am fairly new to the PLI
> but I can talk to and read stuff from VCS. Is there a PLI routine which
> will allow the simulator to be run for a specified time?
>
> - Richard Wilkinson
> Cambridge Silicon Radio UK
From: Petter Gustad <pegu@dolphinICS.no>
It has been a while since I did this but if memory serves me right you call
tf_setdelay with a given delay and you PLI routine will be called with a
reactive message after the given simulation time.
- Petter Gustad
Dolphin ICs Norway
---- ---- ---- ---- ---- ---- ----
From: Srinivasan Venkataramanan <srini@realchip.com>
I, too, am a newbie to PLI and am first focusing on VPI (PLI 2.0) which is
not supported by VCS yet. So the solution that I offer here is more
bookish than through experience. I think what you need is a "way to
synchronize your PLI to the Verilog simulation". In PLI (1.0) there are
"Misctf routines" for this purpose. These could be called due to
several reasons (like endof_compile, end_ofsim, value_change_on_object
etc.) If you have Sutherland's book with you, please refer to Chapter
no. 12 for more.
I think you will need the routines like tf_setdelay (or tf_setlongdelay
etc.) for your purpose.
- Srinivasan Venkataramanan
RealChip Chennai (Madras), India
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