( ESNUG 360 Item 12 ) -------------------------------------------- [11/02/00]
From: Michael Dotson <mwdotson@vnet.ibm.com>
Subject: Design Compiler VHDL Parser Problem with Aggregates In Expression
Hi, John,
I have a piece of VHDL that represents a problem with the DC parser and
aggregates. Strangely enough, the same code is accepted with the VSS,
MTI and Fusion parsers. I was wondering if DC needs help in figuring out
the code without having to rewrite all the code in the first place. This
source has already been built with a different synthesizer but I had a need
to try DC with it. The error msg I get is a VHDL type mismatch from the
expression aggregate because it says the aggregate is std_logic.... which
is bogus because the workaround with temp doesn't have a problem.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (a_vector_1, a_vector_2 : in std_logic_vector (1 downto 0);
a_bit_1, a_bit_2 : in std_logic;
output_1, output_2, output3 : out std_logic_vector (1 downto 0)
);
end top;
architecture arch1 of top is
signal temp_1, temp_2 : std_logic_vector (1 downto 0);
begin
temp_1 <= (1 downto 0 => a_bit_1);
temp_2 <= (1 downto 0 => a_bit_2);
output_1 <= (a_vector_1 and temp_1) or
(a_vector_2 and temp_2);
output_2 <= (a_vector_1 and (1 downto 0 => a_bit_1)) or
(a_vector_2 and (1 downto 0 => a_bit_2));
end arch1;
Both output_1 and output_2 should be equivalent, but they're not! Design
Compiler and Tuxedo both have problems reading in output_2.
- Mike Dotson
IBM
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