( ESNUG 357 Item 6 ) --------------------------------------------- [8/10/00]
From: [ No Names Here ]
Subject: Users Seek DC Hold Fixing Strategies & Insertion Delay Approaches
Dear John,
PLEASE ANONYMIZE THIS MESSAGE: thanks.
I would appreciate hold-fixing strategies from you/your readers. One of our
designs showed up several hold problems between FFs that had no intermediate
logic in the Q-D paths. We're now trying to address this issue in synthesis
land...
The option we're considering is using 'connection_class' in Library Compiler
to prevent Design Compiler from connecting one FF directly to another. This
is obviously a drastic measure, but I couldn't think of another way to
ensure no two FFs were 'directly' connected. Area is not a big concern for
our design, so we're not as concerned with the additional gate count.
- [ No Names Here ]
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From: Ravikanth Nukala <nukala.ravikanth@st.com>
Hi John,
I have a question on Latency (insertion delay). I want to know who exactly
specifies the latency number in the ASIC flow? And how it is calculated? I
am talking with respect to clock tree insertion.
- Ravikanth Nukala
ST Microelectronics
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