( ESNUG 356 Item 7 ) --------------------------------------------- [8/03/00]
Subject: ( ESNUG 355 #9 ) DC, Multiple Clocks, RTL MUXing For Scan Testing
> My design is a multiple clock domain design. In scan mode, however, there
> is only one clock: master_clock from chip pin. In order to balance the
> clocks, I need to MUX all clocks including the master_clock.
>
> wire scan_clk = scan_mode ? master_clk : master_clk;
>
> Design Compiler recognizes that this is feedthrough logic, and thus no
> MUXing logic is generated at all. I talked to Synopsys tech support, and
> was told that there was no way to generate MUXing logic with the above
> code. I seeks for designers' help.
>
> - London Jin
> Toshiba San Jose, CA
From: Allen Brown <allen_brown@agilent.com>
John,
No problem for London. Just remember: hierarchy is your friend.
module part_including_clk_mux ( master_clk1, master_clk2, ... );
input master_clk1, master_clk2;
wire scan_clk;
scan_clk = scan_mode ? master_clk1 : master_clk2;
endmodule // part_including_clk_mux
module container_for_above (...)
wire master_clk;
part_including_clk_mux p1 (
.master_clk1(master_clk),
.master_clk2(master_clk), ...);
endmodule // container_for_above
Now synthesize part_including_clk_mux separately from container_for_above.
You will get your MUX.
- Allen Brown
Agilent Technologies
---- ---- ---- ---- ---- ---- ----
From: Steven Murphy <steven.a.murphy@lmco.com>
Hi, John,
The solution we used was to directly instantiate a MUX from the gate level
library. If you need to balance the delay to the different clock trees then
you will probably have to do the balancing by hand (we did) beyond just
adding the MUX. The clock tree balancer we used (LSI Logic) only handled one
clock domain at a time and did not balance across clock domains. If the
clock domains are of different sizes then the total delay difference through
the various clock trees can be very large. You should estimate the delay
difference now and add some delay buffers to the net list on the scan clock
input to each MUX. Again, directly instantiate gate level cells. These
buffers can then be moved around in the layout to finish the balancing.
Adding them now is much easier than adding them to the gate level netlist.
Also, be careful when it comes to buffering the scan_mode signal going to
the I/O pads for boundary scan. If you let Synopsys do the buffering without
floorplan information then you will end up with a real mess of the same
buffer driving different sides of the chip.
- Steven Murphy
Lockheed-Martin
---- ---- ---- ---- ---- ---- ----
From: Will Leavitt <leavitt@giganet.com>
Hi, John,
Clock control is too important to leave to synthesis. I would instantiate
the exact gates you want in the clock path. This gives you exactly what you
want, and you can give the gates nice repeatable instance names to
facilitate hand placing them during chip layout. Use an ifdef, so that
gates are used during synthesis and RTL is used for simulation, otherwise
you'll kill your simulation speed.
`ifdef synthesis_only
// synopsys dc_script_begin
// dont_touch u_master_clk_mux*
// synopsys dc_script_end
MUX21HC u_master_clk_mux (.A(master_clk), .B(master_clk),
.S(scan_mode), .Z(scan_clk));
`else
wire scan_clk = scan_mode ? master_clk : master_clk;
`endif
Good luck
- Will Leavitt
Giganet, Inc.
---- ---- ---- ---- ---- ---- ----
From: London Jin <jinl@taec.toshiba.com>
To: Will Leavitt <leavitt@giganet.com>
Hi Will,
Thank you very much for your offer. What I tried to avoid is to instantiate
a technology/vendor specific MUX in my RTL code in order to make the code
technology independent and portable in future. The best solution I have
found from solvit is to instantiate a GTECH MUX. I am still not very happy
for this solution either.
Thank you again.
- London Jin
Toshiba San Jose, CA
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
|
|
