( ESNUG 356 Item 5 ) --------------------------------------------- [8/03/00]
Subject: ( ESNUG 355 #17 ) Ways To Convert Xilinx Gates Into ASIC Gates
> I was just wandering if you know what the ratio of the newer FPGA gates to
> ASIC gates is? I have asked Xilinx but they couldn't tell me. I am new
> to the FPGA/ASIC process and am trying to come up to speed. Even a
> ballpark conversion ratio would be helpful.
>
> - Chris Frailey
> Motorola
From: Frank Emnett <frank@aiec.com>
John,
The number I use is about 5:1. Most recently, I had a 200K gate design
(including about 10% memory area) that filled up a Xilinx XCV1000 at 100%
utilization. Didn't use much of its memory resources, though. I've heard
similar figures from at least two other Xilinx users (4:1 or 5:1).
- Frank Emnett
Automotive Integrated Electronics Corp.
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From: Jeffrey Ebert <ebert@sonicsinc.com>
John,
My favorite FPGA metric is the buildable system (BS) gate. Here is a usage
example from the inventor of this metric, Tim Colleran in Electronic News:
"By the way, did I mention that Actel will introduce it's new BS1000M
family next year, the biggest device has[sic] contains one billion
complete and total BS gates. Count them if you can!"
The full article can be found at the URL below, and it is well worth a read
by all your FPGA-using ESNUG readers.
http://www.electronicnews.com/enews/Issue/1999/05171999/20actas.asp
- Jeff Ebert
Sonics, Inc.
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From: Lynn Reed <Lynn.Reed@tekmos.com>
Hi, John,
We have converted about 10 Virtex FPGAs into ASICs. We are seeing the gate
count conversion ratio running close to 1:1 using the Xilinx gate count in
the map.mrp report. This was not always the case. I believe it is due to
several reasons.
1. Better synthesis tools provide greater utilization efficiencies.
2. Increased RAM use in the designs. Small RAMs do not translate
efficiently into ASICs.
3. Increased use of Xilinx cores, such as FIR filters, which are very
efficient in using Xilinx resources.
Regards,
- Lynn Reed
Tekmos
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From: Al Czamara <czamara@asic-alliance.com>
Hi, John.
Here's what I got from the Xilinx staff recently ...
We actually came up with a formula to report an equivalent ASIC gate count
from our mapping tools, the problem is that the formula actually looks at
the actual resources used in an FPGA. So, if you have a design that is
running through our tools, we will (in version 3.1i) report an equivalent
ASIC gate count. It basically assigns ASIC gate equivalents to each of the
elements that might have been used in the FPGA and is therefore pretty good,
but very design dependent. Here are the numbers that we use in reporting
ASIC equivalent gates for our designs:
Frag Virtex ASIC equivalent
gates
---------------------------------------
4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3
I don't know if this helps or not. This is supposed to take into account
ASIC and FPGA routing factors, so you wouldn't need to adjust it in any way.
From my unscientific and very limited experience with the Virtex
architectures, the general rule of thumb that I've used is to take 2/3 of
the FPGA system gates and that roughly equates to ASIC gates (i.e., A V300's
300,000 system gates are about 200,000 ASIC gates). But as you can see,
depending on the design, YMMV.
- Al Czamara
ASIC Alliance
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From: Ted Boydston <tboydsto@harris.com>
Hi John,
We have been converting ASICs to FPGAs for a while now. Typically we have
been seeing 20 Honeywell 0.35u SOI gates per Virtex slice. The spread I
have seen has been as low as 15 and as high as 30, depending on clock speeds
and how full the Virtex is.
If you do some quick math, one can calculate the typical ASIC gates for a
Virtex 1000, which has a 64x96 CLB array:
( 64*96 CLB )* ( 2 Slices/CLB )* ( 20 Gates/Slice ) = 245,760 Gates.
Note that this number excludes block ram, which we typically do not use.
Also, this is purely a Xilinx Virtex logic to Honeywell 0.35u SOI logic
comparison -- your ASIC vendor may differ a bit. If your wondering, as
Harris did, why that number is one-quarter the 1M system gates advertised,
blame Xilinx marketing: they love to include block RAMs when coming up with
that million gate "system-gate" number.
Typically, we divide the Xilinx-marketing-derived "system gates" (Xilinx
Virtex 1000 has 1M such system gates) by 8 to get actual place and routable
"gate array gates" (or about 125K gates). This leaves about 50% of the
device open for design expansion and fixes in the lab. It also provides
routing margin for faster designs. If you are sure that the size of your
array will not change, you could use a divide by 5 or 6 to get the gate
array gate number from system gates.
Xilinx has a detailed analysis of this very subject in an application note
at http://www.xilinx.com/xapp/xapp059.pdf. The application note only covers
XC4000 and XC5000 parts; however, you can extrapolate to Virtex parts
because a 4000 series CLB is almost equivalent to a Virtex slice.
Have Fun!
- Ted Boydston
Harris GCSD
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