( ESNUG 356 Item 4 ) --------------------------------------------- [8/03/00]
Subject: ( ESNUG 355 #2 ) Synchronizers & Timing Problems With Reset Trees
> I have a reset net in my design. I am using "set_ideal_net" command in
> Design Compiler, but I still see huge SN/RN to Q/QN delays in my SDF file
> for any FF connected to the reset net. My design is hierarchical. Does
> anyone know how to take care of this problem?
>
> - Hooman Dadrassan
From: Paul Zimmer <pzimmer@cisco.com>
This problem is probably that the reset net has a very large risetime. His
risetime value doesn't show up directly in the SDF (because SDF is only
delay information), but it shows up indirectly as very long setup/hold/prop
times on flops.
In your case, the slow risetime on the reset is causing the extraction tool
(the one that generates the SDF - I gather you are doing this with DC?)
to predict a long reset2q time.
If you are indeed using DC, you might try doing "set_drive 0" on the driving
cell's output pin and/or "set_resistance 0" on the net. This is assuming
that you have some other fix in mind for the real chip (like using a clock
tree macro).
- Paul Zimmer
Cisco Systems
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