( ESNUG 348 Item 8 ) --------------------------------------------- [3/30/00]
From: Hans Miller Pedersen <HMP@oticon.dk>
Subject: Problem Interfacing Synopsys DesignPower And Cadence NC-Verilog
Hi John !
We are using Synopsys DesignPower and Cadence NC-Verilog, in order to
perform power estimation of our ASIC's - but we are having problems -
perhaps some of your readers might be able to help us out.
The problem relates to the backward SAIF file, written by NC-Verilog
through the $toggle_report PLI supplied by Synopsys (the file contains
switching activity for all ports). It seems like some input ports are
dropped, but not all. When read into dc_shell, and running report_power,
these "dropped input" are having default 50% switching activity (no
annotation), which was the way I initially discovered the problem.
Has anybody discovered similar problems ?
- Hans M. Pedersen
Oticon A/S Hellerup, Denmark
|
|
