( ESNUG 319 Item 5 ) --------------------------------------------- [5/26/99]
Subject: Current Cadence/Synopsys/Avant! Techniques For Verilog Encryption
> I was wondering if anyone knew the status of source code protection/
> encryption for Verilog. I know Cadence and some others have this
> feature but that they were not cross-vendor compatible.
From: Lance Pickup <lpickup@xanadu.btv.ibm.com>
As far as I am aware, source code protection is available via the following
means (this list may not be complete):
1) Most (all?) Verilog vendors provide a source code encryption mechanism
based on use of `protect blocks and the +protect command line arguments.
I know that Cadence Verilog-XL, Chrono VCS and Avant! Polaris all have
this capability. It's quick and painless to protect your source this
way, involving a mere pass through the front-end parser and spitting out
platform independent "encrypted" code. It is also very inexpensive: the
Verilog simulators that support this allow you to use this feature for
free. The drawbacks are:
- There are exposures using these methods. The Verilog-XL encryption
has been cracked in the past. Apparently VCS has a possible security
hole that has been addressed. The moral here is that this is not
an extremely safe method!
- It is vendor-specific. So you would have to encrypt in whatever
simulator the person receiving your source is using. This may
invalidate my comment about cost above if you have to go out and
buy a simulator seat just to protect your models!
2) There are tools available which obfuscate the source -- transforming
module, component, net, port, etc. names into "undecodable" strings of
characters such as IO0Oo000II111iO in an attempt to mask the true nature
of the source. I'll leave it to you to assess the security of this
approach. Still, if you are certain you have non-malicious users and
your source is not incredibly sensitive, this may be a workable approach.
3) There is the VMC tool from Synopsys which compiles your Verilog (with the
VCS engine) into object code. Prior versions output a model with a PLI
interface that would work with any Verilog simulator. The latest version
puts a SWIFT interface on the model which can be used with most popular
simulators, allowing you to share your Verilog model with VHDL users
(without the need for co-sim licenses). The SWIFT interface does not
currently support cycle-based simulators. I am not sure how this relates
to the Synopsys CoreBuilder product.
4) Keep an eye on OMI (Open Model Interface). This is not a current
solution, but is one that is in the works. This is now an IEEE standard
(1499) API for simulators. Cadence and a few other vendors have said
that their simulators will be OMI compliant by year end and Cadence
plans to offer a "packager" utility which will package up models
presumably compiled with one of their simulators). I believe the
packager will come with the simulator and allow you to package models for
free to be used with Cadence simulators. If your models need to be used
with other vendors' simulators, there will be a cost associated.
It is said that OMI will have the capability to support cycle simulators.
- Lance Pickup
IBM Microelectronics Burlington, VT
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