Begin ( Part 1 of 2 )
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "One Sheep Farmer's Impressions Of SNUG'98 & IVC/VIUF'98"
_] [_ (plus what 33 other engineers saw there, too.)
by John Cooley
Moderator Of The E-mail Synopsys Users Group (ESNUG)
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
First Impressions: B.O. & Wally
-------------------------------
The first morning of SNUG'98, the DoubleTree Inn (where the majority of
SNUG attendees were staying) had no hot water. I took this to mean that
God was telling me: "John, go downstairs to breakfast first before going
to SNUG." Later on, my girlfriend told me to her that would have meant:
"Stay in your room until there's hot water. Don't go in public looking
(or especially smelling) homeless." Being a guy, I went for breakfast.
After breakfast, the hot water problem was fixed. Got cleaned up and
went to SNUG. And right at the bottom of the stairs leading to the
SNUG'98 registration desk, I unexpectedly found Wally Rhines, the CEO of
Mentor Graphics, wearing plain clothes along with a mysterious, unknown
man wearing an expensive European cut suit. Huh?
"I'm here to see the next generation of technology."
[ pause listening to an engineer's laughing reaction to this ]
"Make that: I'm here to *present* the next generation of technology!"
- Mentor Graphics CEO Wally Rhines upon being unexpectedly spotted
at the enterance to the SNUG'98 conference
Then Wally tried to pass off that he was going to Japan that day and had
just happened to stay in the same hotel that night. Yea, right. As if
we don't know EDA spies are everywhere! :^)
The Numbers
-----------
Because EDA salesdroids and marketeers are known to distort/exaggerate
what other customers are doing/saying about a particular tool they're
trying to get you to buy, over the years I've found it necessary to get
the hard data myself -- whether it be the ratio of Verilog users to VHDL
users or how many customers attended a specific talk. I found it
interesting that even though I was told there were 20 people in the
"Intro To EAGLE Tools" and 120 people in the "Test Compiler" tutorials by
Synopsys employees, when I checked, I found only 9 & 84 attendees present.
Here are the exact numbers of attendees I personally counted in each talk.
Wednesday, March 11. (Tutorials) Number Of Attendees
8:15 - 11:45 Effective Use Of Logic Synthesis 243
8:15 - 11:45 Protocol Compiler 22
8:15 - 11:45 Synopsys/EPIC For Structured Custom ICs 42
8:15 - 11:45 Design Reuse & DesignWare 54
8:15 - 11:45 FPGA Compiler II & FPGA Express 49
8:15 - 11:45 Module Compiler & Datapath Design 46
1:30 - 3:00 Panel: "High Speed Design" 391
3:15 - 4:45 Panel: "Missing Links In EDA" 326
5:00 - 7:00 Synopsys R&D Cocktail Party over 500
Thursday, March 12. (Main Conference Day)
9:00 - 10:15 Keynote Address (Aart's Speech) 223
10:30 - 11:45 Users on Synthesis & Designs 321
10:30 - 11:45 Users on EPIC Design Tools 41
10:30 - 11:45 # attendees randomly wandering in hallway 29
1:30 - 3:00 Users on Synthesis (contined) 158
1:30 - 3:00 Users on Deep Sub-Micron Designs 132 + 11 standees
1:30 - 3:00 Users on Behavioral Synthesis 58
1:30 - 3:00 Users on FPGA Synthesis 36
3:15 - 4:45 Users on Makefiles, Scripting, Etc. 236
3:15 - 4:45 Users on Chronologic's VCS 78
3:15 - 4:45 Users on Design Reuse & DesignWare 46
3:15 - 4:45 Users on FPGA Synthesis (continued) 34
5:00 - 8:00 Vendor Fair Of Other Company's Tools over 600
Friday, March 13. (Tutorials)
8:00 - 11:15 Chronologic's VCS 44
8:00 - 11:15 Test Compiler 84
8:00 - 11:15 Behavioral Compiler 74
8:00 - 11:15 Power Compiler & EPIC Tools 92
8:00 - 11:15 Memory Verification Models 11
1:00 - 4:15 Design Compiler RTL Coding Tricks 181
1:00 - 4:15 PrimeTime Static Timing Analyzer 108
1:00 - 4:15 Intro To EAGLE Tools 9
Overall, SNUG'98 had 590 registered attendees which matches last year's
count of 600 attendees. On the technical side, last year SNUG'97 had
8 tutorials and 16 user papers. This year, SNUG'98 had doubled in
count to 15 tutorials and 30 user papers.
The Bigwig's Big Speech
-----------------------
This year's keynote was given, as always, by Aart De Geus, the founder
and CEO of Synopsys. I've been Synopsys-watching and Aart-watching for
years. I could regurgitate exactly what Aart said verbatum, or I can
tell you what he *really* said. I chose the latter. (So what follows
are NOT Aart's words or even his style of speaking -- he's far too well
mannered with his European schooling to be this blunt -- but I'll swear
on a stack of Bibles that this is what *I* heard him effectively say.)
1.) "After 6 long years of being mercilessly harrassed by my American
customers, I can now say that not only do I have a Verilog
simulator, I have the badest, meanest, hottest, fastest Verilog
simulator around: Chronologic's VCS !!! It may have cost me
half a billion dollars, but with it, and Design Compiler, and
the entire static timing analysis market, and the entire test scan
market, and a nice piece of the transitor/signal integrity tools
market, plus a hefty chunk of the formal verification market,
Synopsys is going to kick some serious big time EDA butt! Woooo!
Wooo! Wooo! Goodbye, Cadence! Bye-bye, Avant! Wooo! Wooo!"
2.) "We see a gaping, gushing hole in our design flow concerning design
iterations between P&R and synthesis. We're working closely with
IBM to develope new tools (like Chip Architect) around this problem
and we'll be dancing in the trade press over the next year about
P&R tools. We already own 11 percent of Gambit stock, we're openly
talking with P&R start-ups like Everest. Again: Goodbye, Cadence!
Bye-bye, Avant!" (To wit, here's one of Aart's own slides below:
IMPLEMENTATION | VERIF. & ANALYSIS
-----------------|-------------------
| Synthesis | VCS, VSS | High Level
| X X X | X X X |
-----------------|------------------|
| Place & Route | Nano IC (EPIC) | Physical
| X | X X X |
-------------------------------------
Which one of these boxes has only one "X"? Can *you* find it?)
3.) "Ambit put a nice scare into my company, and, as a result my R&D
team has beefed up Design Compiler to be 3X faster, to now handle
100 kgate block sizes with ease, to have a 15 percent improved QOR
via new algorithms, plus offer time budgeting, too. Ambit, do
feel lucky, punk? Huh? Well? Do you?"
4.) "The design reuse game is a little more complicated than what most
people think. We've learned some very hard lessons along the way
and we think we'll do quite well capitalizing on it in the newly
hyped up, burgeoning, booming, ever expanding IP market."
5.) "We're the only big EDA company trying new stuff like Behavioral
synthesis and non-tiling based datapath compilers. We're also
just branching off into HW/SW co-design amoungst other things."
6.) "We dropped ARKOS because we didn't see the hardware emulation
market big enough to profitably support two main players. Sorry."
7.) "Yup, we're doing some design services consulting. Cadence, Mentor,
and Avanti are doing it, so we gotta offer it, too. I don't
see consulting as our core like Cadence does (except maybe in
consulting on how to make portable, reuseable IP) but we'll offer
it. Instead, I see creating next generation EDA as our core - which
is why we spend 24 percent of revenues on R&D - that's the highest
percentage on R&D of *any* software company in or outside of EDA."
Again, Aart didn't really say all of this officially in his talk, but
as a very long time EDA watcher, it's what *I* and many other EDA users
know he said. And, oddly enough, from my own surveys of the Synopsys
customer base, Aart's "speech" above agrees with what most customers are
saying. Aart, in his own way, was refreshingly open & honest here.
The Conference Itself
---------------------
"Technology is part of our fundamental DNA."
- Aart De Geus, CEO of Synopsys
"The hallway conversations seemed to have a lot to do with hiring ASIC
designers, which are very hard to find - especially very experienced
ones. I know that because our company is trying to hire several
hardware people, and it's not easy. I did a bit of asking around at
the coctail parties. Well, what I got were smiles and a warm 'Welcome
to the club!'"
- Oren Rubinstein of GigaPixel
SYLVIA'S NO-TELL MOTEL: When Synopsys customers have really involved IP or
EDA related problems that require that the customer have extended, close
contact with Synopsys R&D, they can check into the unofficially named
"Sylvia's No-Tell Motel" -- a set of 18 separate & secure private offices
on-site at Mountain View. Each office, with room enough for 3 desks, each
has its own private phone line, restroom, kitchen, & outside enterance.
These aren't cubicals; they're separate offices with sealed ceilings and a
customer-settable-only omni-lock to its one entrance. This allows
competitors to bring their own workstations on-site to visit Synopsys for
anywhere from 2 weeks to 3 months & keep their designs secure. Not even
Synopsys employees can get into these offices. Who's Sylvia? She's the
lawyer at Synopsys who created and who runs the "No Tell Motel".
"I think it's because he overheard you're a lawyer. It's a subconscious
thing. It also could be because you're a Synopsys employee, but there
are lots of them around here. Yea, it's probably a lawyer thing."
- Overheard being told to Synopsys VP (and lawyer) Paul Lippe
after a SNUG attendee physically walked into Paul and then
rudely walked away without even acknowleging Paul's existance
"ALL RESISTANCE IS FUTILE!": Borging into the memory modeling business,
once the exclusive domain of Denali Software, the Synopsys Logic Modeling
Group annouced "MemPro" -- a memory model generation tool -- at this SNUG.
"My Irony award goes to the group handing out questionnaires on
security and how much we trust Synopsys with our IP. The reward
for filling out the questionnaire was a pad-lock, with "Secuity
is Key Synopsys" silk-screened on. However, the "lock" opens
by pulling on it. No key or combination needed!"
- Anon
SHINING PATH MAOIST GUERILLAS: Last December, an Intel engineer publically
endorsed the Synopsys datapath synthesis tool called Module Compiler.
(This was quite interesting because Intel never endorses *anything*.) In
a surprize reply, an engineer from LSI Logic actively voiced a 28
paragraph dissenting view of Module Compiler that advocated the use
of TeraSystem's TeraPath tool instead. This, in turn, triggered a 54
paragraph avalache of support for Module Compiler from engineers at
Silicon Graphics, IBM, Hewlett-Packard, Motorola, NVidea, S3, Tensilica,
and Alpine Semiconductor. What's interesting about this isn't the wide
popularity of Module Compiler as much as its basic approach directly
opposes the much touted "Higher Levels of Abstraction" philosophy so
swooned about with Behavioral Compiler. It's as if datapath synthesis
is a populist guerilla movement within a Synopsys dedicated against it.
("Shining Path Maoist Guerillas, John?", you ask. They're leftist rebels
active in Peru. And while 46 users went to the MC tutorial and 74 to
the BC tutorial, the ultimate spoof is that, either way, datapath or
behavioral, Synopsys wins because they sell *both* approaches.)
"This tool is cool. We came up with 8 different variants of a mammoth
pipelined multiplier (*really wide*) within a week including 1 day of
instruction and a day of learning curve. Something like this would
have taken months to develop and we were able to go back to management
and say "here's a matrix of size vs. performance with our various
implementations". Never saw a manager's jaw drop so fast when we
were able to provide a real close gate count and performance eval."
- An Intel Engineer discussing Module Compiler in ESNUG 275
"To twist an infamous quote from a former EDA CEO -- if Synopsys put a
DogFood Compiler on the market, would users be sending ESNUG
testimonials about how tasty the gravy bits are?"
- The ESNUG 279 opening to a 28 paragraph reply from an LSI Logic
engineer dis-ing Module Compiler & favoring Tera System's tool
"When that LSI guy said 'Hell -- us real designers don't even use
standard cells, we design the whole chip at the transistor level for
breakfast.', I had to laugh. As a 'real designer', I would rather
spend my time developing innovative architectures quickly and getting
them market as fast as possible. And that's what Module Compiler
allows a designer to do for arithmetic intensive designs."
- Bob Prevett of NVidia (in ESNUG 280) in a reply to the LSI engineer
"Had an extended discussion with the Behavioral Compiler folks about
the 'quality' of their documentation and the code examples at the
R&D Cocktail party. The Synopsys guy must have been well into the
punch bowl, because he (actually) said 'Dude, those docs suck. They're
useless.' He promised to send me some greatly improved but not yet
released docs, and has, in fact, already started following through."
- Anon
"It seems to me that Synopsys doesn't push behavorial synthesis as I
thought. Most of the presentations were about RTL synthesis, new
tools, coding techniques,... And in their paper, the fastest BC design
that they present runs at 66 MHz. I think they don't pretend
(anymore ?) BC can do as good as with 'normal' synthesis."
- Anon
"HE'S BAAAAAAAAAAAACK!": With much fanfare four years ago, Synopsys
annouced its first serious large DesignWare part, the DW PCI. A year
later, after being booed by the angry customers who bought it and found it
didn't work, Synopsys pulled the infamous DW PCI from the market. Now,
after three years of some behind the scenes work, Synopsys has come back
into what is now called the IP market with a DesignWare PCI part along
with a completely new approach to how IP is created and used. Anonymous
sources have shared that this new approach is code named "AppBuilder
Developer" for the creation of IP and "AppBuilder Player" for the use of
the IP. Here's a list of the known processes and speeds that work with
the new Synopsys DesignWare PCI part:
Library vendor/size: (PCI speeds in Mhz)
LSI Logic 0.5 : lca500k (33)
LSI Logic 0.35 : g10 (33 & 66)
TSMC 0.5 cba : (33)
TSMC 0.35 cba : (33 & 66)
IBM 0.35 : (33 & 66)
IBM 0.35 cba : (33 & 66)
Lucent 0.35 : (33 & 66)
Lucent 0.25 : (33 & 66)
The timing is from the maximum configuration in each libraries (64-bit PCI
and application, lots of BARs, etc). Also, 66Mhz timing has full scan
insertion. Burnt once, a lot of customers are curious yet cautious here.
"My company has had considerable experience with Synopsys's PCI
product, most of it quite bad. Their basic problem was using a
group of software developers to essentially design hardware while
learning hardware design on the fly. They clearly had no
experience with logic design at this level of complexity and
this shows in the quality of their current product, as it's far
from functionally correct."
- An Engineer's DW PCI story from 3 years ago (ESNUG 229)
"As a dog returneth to his vomit, so a fool returneth to his folly."
- Proverbs 26:11 (King James Version)
MONTY PYTHON "RUN AWAY! RUN AWAY!" AWARD: After much bravado & showboating
in the press of it's Arkos emulation technology and how they were going to
blow the competition out of the water, Synopsys very abruptly did an
about-face immediately after DAC'97 by selling it's Arkos division to its
emulation arch-rival Quickturn. It's said that Quickturn got Arkos for
a song, but that Synopsys went to great lengths to insure that the few
customers foolish enough to have bought an Arkos box weren't left stranded
(techincal support-wise) afterwards.
"I wasn't happy at all when it first happened. We invested in them!
We trusted Synopsys! Bah! But after the hand-off the Quickturn people
were supportive of us, unexpected for a customer who had earlier
decided against buying their box."
- An ex-Arkos customer
"That changed my tune when I had to breathe our own exhaust. That,
and learning that P&R is another form of Hell."
- An ex-Arkos R&D Engineer describing using Synopsys and other
EDA tools to design Arkos hardware
DISRUPTING THE PAX ROMANA: When medieval scholars felt depressed they used
to reminisce about the great Pax Romana (literally "Roman Peace") which
allowed peoples from Britannia all the way to Byzantium to speak one
universal language, have one law, and to trade freely. In the EDA world,
the monopoly on ASIC synthesis created a sort of "Pax Synopsae", where all
ASIC designs passed under the watchful aegis of Design Compiler. And each
time when Synopsys faced a challenger to Design Compiler, Synopsys crushed
it with Roman Legions of Salesmen, Marketeers, & Apps Engineers.
IBM EDA, the EDA world's equivalent to the The-Gang-That-Couldn't-Shoot-
Straight, couldn't even get *one* non-IBM customer to buy "BooleDozer".
Even though Wally Rhines was a bigwig at Texas Instruments before becoming
the CEO of Mentor Graphics, his old TI buddies ended up buying Synopsys
synthesis because Mentor's "Autologics II" fell on its face in the internal
TI benchmarks. Cadence tried to float "Synergy" out onto the market, but
nobody took them seriously. The same happened with Veribest & with ACEO.
And although there's a lot to be said for universially accepted EDA tools
yada, yada, yada... one sad side effect is that there's no drive to make
things better. That is, until "Hallelujah!, All Praise Be To Jesus!",
Ambit came along with its BuildGates synthesis tool. Ambit has too many
good connections to be killed off by the usual Synopsys Sales & Marketing
Roman Legions. (The CEO of LSI Logic, Wilf Corrigan, has stock in and is
on the Board of Directors of Ambit and Ambit's CEO, Prakesh Bhalerao has
close ties with Toshiba from his Silcon Architect days.) "Oh, shit, boys,
it looks like it's going to be *technology* that wins or loses this war!"
And this has been fantastic for Synopsys. It took a normally complacent
"let's-fix-the-bugs" Synopsys synthesis R&D team and put fire in their
bellies. Instead of <yawn> just incrementally improving Design Compiler
in a "safe" way that doesn't rock the boat too much inside Synopsys, it
suddenly became Priority Nombre Uno to Do-Whatever-It-Takes-To-Keep-
Design-Compiler-A-Killer-App. Whoa! Cool!
Now, Design Compiler 98.02 can handle design block sizes of 20 to 100
kgates instead of the old 4 to 10 kgate limit. DC 98.02 converged 1.39X
to 5.11X (with an average of ~3X) faster than 97.08 (and an average 13X
faster than 3.4b) for the 110 designs in the internal Synopsys convergence
benchmarks. This means Design Compiler runs are now 3X faster.
The subset of Verilog/VHDL that is now synthesizable to gates has expanded.
DC 98.02 also has handy new optimization algorithms including:
Pin-swapping
Latch time-borrowing
Implementation selection
Gate-composition for area
Multiple-port net fixing
Critical_range and delay optimization algorithms
This all munges together to where of the 156 designs in the internal
Synopsys QOR benchmarks:
103 (66 percent) got a better QOR which averaged a 13 percent speed-up
(with the best being a 17 percent speed-up)
37 (24 percent) remained the same speed-wise
16 (10 percent) got a worst QOR which averaged a 6 percent slow-down
(with the worst being a 15 percent slow-down)
So for the 90 percent of designs, QOR got noticeably better or remained
the same. That average delay reduction of 13 percent is bigger for slow,
large designs and smaller for tiny, fast ones. (i.e., it helps the worst
things the most.)
You can now use multibit components. (This is like the "size=n" property
in Valid, for all you old farts.) The library must support this with
sized components of the value desired. (i.e. 8 flops in a bunch, 4 wide
2:1 MUXes, sets of tri-states, etc.) This can allow you to create regular
multibit structures.
Timing exceptions are more flexible. They can go to a particular pin,
rather than just the component. You also now have support for
simultaneous Min/Max compiles. This is enabled if you use set_fix_hold.
(Remember to specify both libs, else you will get the default for both.)
And even though there's a nest of new commands and options, my personal
favorite is that many "set" commands now have a "-through" option! Yes!
The ulitmate irony here is that, from what I've seen, Ambit's BuildGates
is a fairly basic synthesis tool. It has a schematic viewer that lets
you directly edit gates by hand (with retiming built in), a hierarchy
browser, a fast timing analyzer that uses IBM's Delay Calculating Language,
and it has the user throwing raw synthesis transforms (stuff like "intial
map HDL to gates" and "increase buffering") along with a standard TCL
interface. Nice, but technologically very basic stuff that essentially
makes synthesis results very, very user dependant. (That is, a highly
skilled user of BuildGates can get great results -- but a skilled user of
most *any* EDA tool can get great results. The question is what will the
average Joe Engineer get? And it's there where I have my doubts.)
In terms of market penetration, from the best I can put together, Ambit
has sold 20 to 35 single copies of BuildGates to 20 to 35 different
companies. (Synopsys has sold about 9,000 copies of Design Compiler, thus
Ambit has a 0.38 percent market share.) And so far, these customers have
been curious customers -- not using Ambit to actually design anything.
(In contrast, an estimated 25,000 designs-to-tape-out have been done with
Design Compiler.)
I've asked Ambit a few times to name *anyone* who's using BuildGates for
actual designs and they just reply: "We can't tell you, but it *is*
being used for real designs!" But I do personally know customers who
have cleverly used Ambit as leverage against Synopsys in sales
negotiations to buy more copies of Design Compiler or to get better
customer support from Synopsys. Library-wise, I think only LSI Logic has
announced it will create BuildGate libs; in contrast, I think something
like 70 ASIC vendors provide around 350 libs for DC.
So, at a year out, Ambit doesn't appear to be a real threat to Synopsys;
but it's put the Fear of God into Synopsys making them now *very* customer
and technology driven. I love it, because, either way we users win! (And
I wouldn't be surprised to learn years from now that Aart De Geus had
secretly seed funded Ambit to re-invigorate his Synopsys R&D team. It's
worked nicely. Cool.)
"It looks like it's time to switch to 98.02."
- Anon
"Let's see... 3 years? It only took them 3 years to get multibit
components? 3 years?"
- Anon
THE SHORT LIST: This year, 26 other EDA vendors came a peddling their
their wares in the frentic 3 hour long SNUG Vendor Fair. That list, A
to X, was: Altera, Analogy, Applied Microsystems, Aptix, Artisan, Avant!,
Cadence, Design Acceleration, DEC, Escalade, HP, IBM, LogicVision,
Lucent, Mentor Graphics, PADS Software, Quickturn, Summit Design, SUN,
SVR, Teradyne, Ultima, VeriBest, Versity, Ward Davis, & Xilinx.
"Spent some time chatting with the folks from Artisan; you give them
your layout rules and Spice models, and 3 months later they hand you
a complete set of library models and a RAM generator. The RAMs have
flip-flop like timing, run wicked fast, and even include such niceties
as embedded bypass for test. Did I say we could have the goodies
in 3 months?"
- Anon
"What's hot? The AT&T guy has an FPGA with a built in 66 Mhz PCI
interface and 48 kgates of programable gates. Parts # OR3TP12
-5BA256 (256 pin BGA) and OR3TP12-5PS240 (240 pin QFP). There are
no data sheets because they're not out until August."
- Anon
"Xilinx touted their new software, which is just repackaged Synopsys
stuff, and announced the imminent arrival of their first million (dog)
gate FPGA. They have no technology for partitioning a design amongst
multiple FPGAs. Altera was also there, and they claim that specific
feature now works well (it didn't for [Project Name Deleted].) The
guy I talked with basically admitted that their FPGA (dog) gate
capacity simply outran their software's ability to handle it. Having
that knowledge up front would have saved us a bunch of headaches."
- Anon
"Protocol Compiler - Just released last month, this is the Synopsys
equivalent of Summit's Visual HDL for protocols. It allows you to
define a protocol in pictures, where you have boxes in each timeslot.
Inside the box, you scope down to other boxes and eventually define
some signal activity."
- Anon
"The other highlight was Summit, who was showing a Verilog simulator
that had a live display of a psuedo-schematic representation of the
netlist. This would have saved hours and hours and maybe even
days while debugging [Project Names Deleted]. Someone alleged that
Undertow could do something similar, which I will attemp to verify."
- Anon
MOTIVE & PRIMETIME: One of the business coups this year for Synopsys is
that it now completely owns the static timing analysis market from its
purchasing ViewLogic. Because there are quite a few die hard MOTIVE
users, rather than repeat the ill-fated Cadence/Valid merger where the
Valid customers staged an open revolt, scuttlebutt has it that Synopsys
is going to support two more revs (one year) of MOTIVE plus all the
already scheduled requested customer enhancements to MOTIVE.
"DAMN IT MOTIVE WORKS! WHY FUCK IT UP WITH SYNOPSYS?"
- One MOTIVE user's initial e-mail to the Viewlogic buyout
"At the R&D Cocktail party, the PrimeTime folks were happy to meet an
actual user, and handed me a t-shirt to express their gratitude."
- Anon
"I also attended the static signoff tutorial. It was actually humorous
since everyone in the audience (for the static timing part) wanted to
know if this was such a good analyzer and helps with synthesis, why is
it not part of DC."
- Anon
THE JURY IS STILL OUT: Last year at SNUG'97, Aart let slip that Synopsys
was working on a formal verification tool. Although it didn't bode well
for Chrysalis at the time because Formality (the Synopsys FV tool) turned
out to be another equivalence checker; a year later Formality is just now
being tested and questioned by ASIC designers. The recent ESNUG 283
yielded a user letter that DEC had used Formality in a 2 million gate
design. But it also had a letter from Ericsson and another very
techinically detailed anonymous letter both openly questioning the real
usefulness equivalence checking FV tools in chip design methodologies.
While such notable companies as SGI and Nortel endorsed equivalence
checking a few years ago, it appears that today's customers are still
undecided about this approach.
"Formality seems to be a 'we also have' product. I didn't catch
anything in their presentation that made me think that they would
be any better than Chrysalis. I guess the name recognition of
Synopsys will help the formal market a great deal."
- Anon
TEST COMPILER & SUNRISE TEST: Another business coup from the Synopsys
buyout of Viewlogic is that it nows own a very high percentage of the
test market now. Test Compiler is well known for full scan applications;
Sunrise has a great rep for partial scan. It's unknown how the two
tools are going to be handled as far as their users are concerned, but
their R&D staffs are being morphed together into one very testy team. :^)
"Power? We don't need no stinkin' power! All the neat tricks you
and/or Power Compiler can do conflict with our DFT requirements,
so anyone interested in all the things we can't do is welcome to
read the Intel paper on it."
- Anon
IF YOU CAN'T BEAT THEM, BUY THEM: The big coup for Synopsys out of buying
Viewlogic is that they got the much lauded compiled Verilog simulator
from Chronologic called VCS. According to Dataquest, VCS had about 20
percent market share in FY 1996 with Cadence owning about 65 percent.
VCS is bound to increase its market share now that it is teamed up with
the 90+ percent market share synthesis tool Design Compiler. The
embarrassing story behind the story is that Synopsys had been working on
a VCS-like compiled Verilog (Code Named "Vivachi") but it couldn't keep
up with VCS in secret customer benchmarks. The big hoopla that Synopsys
made about the even newer improvements to VCS 4.1 (like 2X speed-up, 1/5th
memory useage, & single reads of SDF files) were in the works all along.
"Each time we caught up with VCS, they came out with a better
version which beat us. It was very frustrating because we couldn't
come out with a Verilog that just matched VCS. It had to be better."
- Synopsys Anon
"The author suggests going after verification with as many different
tools and as many cycles as possible. (No, he didn't offer to pay for
it.) An interesting point was the use of "Ratify" (Rat Compiler?)
which is a Verilog->VCS preprocessor which will be available from
Synopsys this summer as part of VCS."
- Anon (discussing the SUN UltraSPARC verification user paper)
PGP FOR IP: Yet another gem from Synopsys gobbling up Viewlogic (and
Chronologic) is VMC, a tool that converts Verilog based IP into raw,
accelerated machine binary. What this does is effectively encrypts the IP
yet keeps the IP executable by customers (and ironically, a side effect is
that the encrypted IP now executes 3x to 5X *faster* than in its orginal
form running on Verilog-XL!) That is, Synopsys now owns one mother of a
security system for IP vendors.
"ONLY THE PARANOID SURVIVE": The last nugget for Synopsys snarfing ViewLogic
is that it got Quad Design's nest of signal integrity tools and whizkids.
From what I've heard, they're being married to the Synopsys EPIC guys, but
details are scanty, which is classic EPIC. EPIC, as far as I can piece
together, has around 1500 to 2000 very ultra paranoid customers marooned
in little very isolated islands amoungst the major Big Chip houses. The
irony is that all these customers are doing exactly the same thing, but
they somehow think that they're the *only* ones thinking power & pipelined
designs -- hence extreme paranoia. When they do talk, they say they loved
EPIC tools until the recent rev 5.1 came out. Now it's bug wars until 5.2.
"If competition is chasing you (and they always are -- this is why 'only
the paranoid survive'), you only get out of the valley of death by
outrunning the people who are after you."
- Ex-Intel CEO Andy Grove in his book "Only The Paranoid Survive"
"On the Mill Brothers in general: The pre-5.1 foundation of the mill
products is very strong. We had few proplems with the tool unless we
started using complex memory structures or EEPROM structures (structures
that use *very* sensitive voltage references for switching purposes,
they tended to trigger at the wrong times). ... Post-5.1: ACE is a
great improvement for the tool set. They really needed to get
near-HSpice-accuracy into their tools, especially when Avanti
snatched-up HSpice *and* ADM (ex-anagram). I've evaluated ACE and
I'm very happy with both speed and accuracy, both for digital and
analog applications. Unfortunately, Synopsys really screwed up the
release of 5.1 (QA? I heared one AE describe the QA people as "qualified
assholes"!) The CDs out of the box couldn't even be installed, once
that was patched, most of the advanced digital stuff (ADFMI) was
non-operative. We helped identify and get repaired about 1/2 dozen
bugs (some were show-stoppers, such as OpAmp gain suddenly becoming
one!) but most were fixed quick. They still need to repair a problem
with their Save/Restore State feature, and the fact that you can't
print their manuals. It's bug city central."
- Anon EPIC user
CHECKING THE RECORDS Not liking the Sea Of Too Much Information one
commonly gets from the reports generated by EDA tools like DC, BC, and
MOTIVE, David Black of Qualis presented a free tool he created called
"LogScan" that greps out the real information you're interested in
gleaning from those reports. Many SNUG'98 attendees voiced interest in
using his free LogScan script. (David's e-mail is dcblack@qualis.com)
"Oh yeah, I found Tom Harrington's Synperl to be a good, general-purpose
tool that I am definitely going to borrow. I, too, took the dc_perl
approach (I didn't know dc_perl existed) and would pipe commands to
dc_shell. I really like the perl-centric approach because it seems
that it may be easier to change things under the covers if a new tool
becomes best-in-class and you want to migrate."
- Engineer George Zalewski of Allen-Bradley (Tom Harrington's
e-mail is "tharring@ford.com" if you want a copy of Synperl.)
CLEANING HOUSE IN VHDL: Johan Sandstrom presented a synthesis pre-processor
for VHDL that caught the eye of many VHDL-based designers at SNUG'98. This
free tool translates higher level VHDL into synthesizable code and checks
for synthesis vs. simulation, nonsense constructs, and nonsynthesizable
on your VHDL. It also adds pragmas where needed (translate off/on) and
evaluates percent of code which is comments. If you want a free copy of
PreSynth.vhd, e-mail "johan.m.sandstrom@mcimail.com".
"From the panel, here is a list of choices for speedup, according to
one of the EXPERTS:
rearchitect HDL source
revert to Gate Level Spec
script based transforms
manual rescheduling
auto rescheduling
manual register balancing
auto register balancing
module compiler
change compile strategy
regroup logical hierarchy
rebudget delays/load
design space explorer
improved blah blah (couldn't take notes fast enough)
tweek the netlist
Try setting max area to just smaller than the size of the design.
Somebody had better results with that, rather than setting it to 0.
Check ESNUG post #141 for a description of how to build your own
wireload table. You'll want to take note of whether or not your
wireload models that you use were built with an enclosed or segmented
analysis."
- Anon
"DO THE RIGHT THING": No, it's not the Spike Lee movie by that title, but
the name of a Perl program, by Steve Golsen and Kurt Baty, which you start
up in your Verilog directory and specify the name of your top level block.
You also supply a top level constraints file. From that it will basically
figure out everything it needs to know about your lib, design hierarchy,
timing constraints on your blocks, etc., and perform a bottom up compile
with all required constraints. Cool! It was proven out on a complex 400K
gate design. Do_The_Right_Thing got the SNUG'98 "Best Paper" Award. To
snag a free copy of it (encapsulated with free "dc_perl"), via anonymous
ftp go to "ftp://ftp.ultranet.com/pub/sgolson/dc_perl".
For those in the know, there's a subtle double entendre in the naming of
the Do_The_Right_Thing script. Two years ago, Len Lapadula got the SNUG'96
"Best Paper" Award for his work at Lockheed-Martin on a set of simular
Synopsys scripts called "Autosynthesis". Quite a few users that year
complained that although Len's paper won, none of his code was published.
Len had joined Synopsys, Synopsys bought the rights to his work from
Lockheed-Martin and they're running an "RTL Sign-Off" synthesis service
based on "Autosynthesis". By offering a simular script that's FREE to all
Synopsys users, Steve and Kurt are now "doing the right thing"! :^)
"The best part of the R&D cocktail party was the food service; instead
of the traditional buffet, they arranged it in a circle. This really
seemed to confuse a lot of people, and it was quite humorous to watch
clusters of engineers walking all the way around the circle, sometimes
more than once, trying to find the onramp."
- Anon
DEMANDING EQUAL TIME: Howard Landman of Toshiba made a historical "first"
in the SNUG proceedings by having the first paper to have a *rebuttal*
from Synopsys in the conference proceedings. Howard's paper showed the
unpredictable behavior of Design Compiler when it's over-constrained via
some very extensive benchmarks. (Essentially, if over-constrained, DC
produced designs that varied by as much as +/- 5 percent timing-wise.) He
also explored DC's "banana curve" (the "area vs. delay trade-off curve")
and how users can get caught in local minima while synthesizing. The
rebuttal from Synopsys was to show how these metrics have changed with
98.02. (It's also been rumored that Synopsys tried to kill Howard's paper
because it orginally had Ambit benchmarks included. It was through the
intervention of the SNUG'98 president, Don Mills of Lockheed-Martin, that
Howard's paper was kept -- with the Ambit data removed.)
"I encourage you to view the slides at the SNUG website. Howard
basically demonstrated what many intuitively felt; when pushing
performance, Synopsys goes non-linear. Synopsys has been using the
results of Howard's work to reduce this unpredictability, and they
claim some of the improvements in 98.02 result from this."
- Anon
"HELP ME, OBI-WAN KENOBI" In Luke Skywalker / Darth Vadar terms, I must say
that I felt a tremor in the Force at the end of SNUG'98. What made this
year's SNUG so successful was the healthy tug-of-war between Synopsys users
and Synopsys. For the first two years of SNUG, Synopsys couldn't get any
users to volunteer to be on the SNUG board because it was widely held that
SNUG was just going to be a glorified multi-day marketing pitch. What
changed that was some very vocal users speaking out against allowing *any*
Synopsys sales/marketing people at SNUG plus Synopsys agreeing that SNUG
would remain user-driven. Six years went by with users being the driving
and deciding force, and with Synopsys providing lots of the labor. This
year, Synopsys has provided a full time person to keep all the details of
SNUG on schedule. This has worked quite well, and with the continual
guidance of this year's SNUG chairman (Don Mills of Lockheed-Martin),
SNUG'98 remained user-driven. What has caused some concern for me is at
the end of each SNUG, there has been a six year tradition of users
gathering at the last breakfast to openly discuss what worked, what
didn't, what users wanted to see next year, and to volunteer to be the
SNUG board. They would always annouce the meeting in the SNUG closing.
This year, it was unilaterally annouced (to some users surprise) that
they weren't going to have this open, roundtable discussion any more. My
fear is that now that SNUG's a 'happening' user group meeting, is Synopsys
going to quietly try to remake it into a marketing-driven event rather
than a user-driven meeting of minds? I certainly hope not.
"In the councils of government, we must guard against the acquisition
of unwarranted influence, whether sought or unsought, by the
military-industrial complex. The potential for the disastrous rise of
misplaced power exists and will persist. We must never let the weight
of this combination endanger our liberties or democratic processes.
We should take nothing for granted."
- Former five-star general and two term US president, Dwight D.
Eisenhower, in his last State of the Union address
End ( Part 1 of 2 )
===========================================================================
Trying to figure out a Synopsys bug? Want to hear how 6,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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