!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "One Sheep Farmer's Impressions Of SNUG'97"
_] [_
by John Cooley
Moderator Of The E-mail Synopsys Users Group (ESNUG)
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
[ Editor's Note: As a personal challege, I've decided to make this year's
trip report a mix of what users experienced at SNUG plus whatever
I could dig up on Synopsys using my own resources. I'm proud to say
that what you'll find here, you won't find in any "EE Times" or
"The Wall Street Journal" article (yet). It's all new news. And what
these discoveries told me is that when Aart De Geus (the CEO of Synopsys)
brags about his company investing 24 percent of revenue (that's 24
percent of roughly $400 million in 1996), he wasn't kidding!
Also I want to thank & warn the small army of Synopsys users who helped
on this project: when reports like these go out, sometimes the Synopsys
sales force will go after every customer they know who has worked on a
leaked topic telling them: "We *know* you're the one who leaked this
story because you're the only customer using it." DO NOT BE FOOLED BY
THIS TRAP! Synopsys likes to give customers the illusion that they're
the only one using a new product; in reality, Synopsys tends to test
products with groups of customers. Forewarned is Forearmed! - John ]
The Bigwig's Big Speech
-----------------------
This year's keynote address was given by Aart De Geus, the CEO and one of
the founders of Synopsys. Aart is kind of different from many American
high tech CEOs in that he really understands the technical nuts and bolts
of what his company sells. (Many American CEOs are MBA/Financial types;
great for sweet talking Wall Street but fairly clueless about the
technical subtleties of what their company does.)
Aart's speech had an almost professorial tone to it in that it covered
the history of Synopsys and overall industry trends. Synopsys is now 10
years old and has 2,048 employees at 48 locations worldwide. Over 150
of the employees are Applications Engineers or Customer Support staff.
Synopsys made 397.4 Million dollars last year.
Aart saw the following seven major industry trends:
1.) Size/Complexities of ICs Growing 10X every 6 years. (Moore's Law)
2.) Speed Of ICs Growing 10X every 8 years. (More Moore?)
3.) Power Consumption Of ICs Growing 10X every 6 years. "Obviously
this can't continue or hand held devices will cook your hands!"
4.) The Cost Of Building New Fabs Is Becoming Prohibitive -- companies
aren't considering building their own fabs any more -- instead
they're concentrating on making their own special IP and farming
out the actual fabrication process.
5.) The Number Of Test Vectors For A Typical IC Is Growing 1000X
every 6 years. This is unsustainable as a design technique and
is pushing EDA companies to work towards other design verification
techniques like Formal Verification, etc.
6.) System-On-a-Chip (SoC) is coming soon for most IC designers. "In
the past, Intel would sell CPUs; now they're selling MMXs which
are CPUs + Modem Control + Ram Buffering in one IC." Putting
together new and old IP will be the way many ICs will be designed.
7.) Future Products Will Be "Computer + Communication + Consumer"
("C + C + C").
Aart cited a recently designed hand held Nokia Personal Communication
device that gave consumers a link to the Internet as the embodiment
of these seven trends. It's a low power, high speed, System-On-a-Chip,
"C + C + C" design that used old IP (a 386 uP) in combination with
Synopsys/SiArc's CBA technology that was fabbed outside of Nokia.
Towards the end of his speech, Aart introduced how the EPIC acquisition
nicely meshes with the Synopsys product set (especially with the Synopsys
/SiArc CBA technology) because it brings in a whole slew of transitor-level
tools that Synopsys needed to offer customers. Aart closed his speech
discussing how the Synopsys' next major technology step will be to work
with Toshiba and IBM on incorporating IC placement information earlier
in the design cycle.
The Numbers
-----------
"As a customer, I'm really happy to know they wash their hands
afterwards. I wonder if it is Synopsys policy or something."
- An audence member's comment after a Synopsys employee had gone
to the bathroom inadvertantly wearing a live radio microphone.
"Wow. SNUG has grown. It used to be that every third person here
was a SUN engineer. Now it's getting a broad mix of companies."
- Overheard from an attendee during a break.
Quite a few people expected this year's SNUG to have a fairly flat or
even possibly lower attendance than normal because this is the first
year SNUG was held not next to the OVI/VIUF conference. Instead, this
year's SNUG *grew* by 100 to a total of around 600 attendees. Here are
the numbers I personally counted in each session:
Wednesday, Feb 19. (Tutorials) Number Of Attendees
2:00 - 5:15 Evolution Of Design Compiler" 34
2:00 - 5:15 Cycle-Based Verification W/ Cyclone" 36
2:00 - 5:15 Behavioral Synthesis Concepts" 54
2:00 - 5:15 RTL Recoding Tricks For Performance" 274 + 9 standing
5:00 - 7:00 Synopsys R&D Cocktail Party
~ 400 users + ~ 115 Synopsys R&D + ~ 35 Synopsys AEs
Thursday, Feb. 20. (Main Conference Day)
8:45 - 10:00 Keynote Address (Aart's Speech) 407
10:15 - 11:30 Synthesis / Design Productivity 361
10:15 - 11:30 High Level Verification 72
1:30 - 3:00 Higher Levels Of Abstraction 108
1:30 - 3:00 Deep Sub-Micron Designs 224
1:30 - 3:00 Silicon Vendor / IP Panels 106
1:30 - 3:00 EDA Partners (In-Sync) Presentations 24
3:15 - 4:45 Makefiles & Synthesis Scripting 161
3:15 - 4:45 Design Reuse 86
3:15 - 4:45 Silicon Vendor / IP Panels 88
3:15 - 4:45 EDA Partners (In-Sync) Presentations 31
5:30 - 8:00 Vendor Fair Cocktail Party over 500
Friday, Feb. 21. (2nd Tutorial Day)
8:00 - 11:15 Evolution Of Design Compiler 93
8:00 - 11:15 High Performance Verification W/ ARKOS 21
8:00 - 11:15 "HDL Advisor" Methodology & Techniques 88
8:00 - 11:15 Applying Behavioral Design Techniques 69
MEAT & POTATOES BEATS GOURMAND DINING: The interesting insight in this
data is that "meat and potatoes" topics like "RTL Recoding Techniques",
scripting and the synthesis of very large designs (i.e. the "Synthesis/
Design Productivity" and "Deep Sub-Micron" discussions) easily got the
lion's share of attendees as compared to the "new stuff" talks on
ARKOS/Cyclone/Behavioral Compiler. The only place where this trend seemed
to errode a bit was with "Higher Levels Of Abstraction" and the "Silcon
Vendor / IP Panels" on late Thursday afternoon.
"How come there were no papers on Behavioral Compiler? At the Applied
Behavioral Compiler Tutorial (which was _excellent_ btw) they mentioned
about 50 companies worldwide using BC. Yet only one chip taped out
so far! How can this be? Do companies really spend $150K on a tool
and then not use it? Does it really reduce the time to market?"
- An anonymous user's response
Quite a few of the very experienced Design Compiler users also voiced that
they liked the "Evolution Of Design Compiler" tutorial because it pushed
them to start using some of DC's newer features.
DEATH TO SALESMEN & MARKETING PEOPLE: The overwhelming majority of
Synopsys customers at SNUG said they very much liked the fact that no
Synopsys sales or marketing people are allowed to attend SNUG.
"Nice parties, and I DO like to meet the R&D folks. And it's a damn
good idea to protect SNUG attendees from the Synopsys sales people."
- Engineer Oren Rubinstein of Hewlett-Packard (Canada).
"I see my Synopsys sales weenies enough as it is. :^) I'm glad
they're not at SNUG because it keeps SNUG purely a _user's_ group
instead of another one of many Synopsys sales conferences."
- Engineer Gregg Lahti of Cirrus Logic
"OK! OK! I hang my head in shame."
- Consultant Kurt Baty after being chastised for suggesting that
some Synopsys Sales & Marketing staff be allowed to attend SNUG.
(Ironically, two days earlier, Kurt had said how he was "never
going to go to the HP Design SuperCon again because it had too
many marketing/sales people there.")
WHO'S ON FIRST?: Although the R&D Cocktail party was very popular with
the Synopsys customers (because it gave them a chance to interrogate
the person who wrote the EDA tools they're using), it was also the biggest
source of frustration for users at SNUG. The basic problem was that all
the Synopsys R&D/AE people were wearing screwy badges that made sense only
to Synopsys bureaucrats. "Sue Moo, Design Reuse Group", "Ralph Malph,
Design Tools Group", "Bob Mob, Verification Systems Group" -- who do you
talk to about a Design Compiler problem?, an LMC model problem?, a VSS
problem?, a DesignWare problem?, a DesignWare Developer problem? Huh?
"I felt like I was playing twenty questions trying to find the person
for my problem. If I wanted SolvIt, I would have stayed home."
- One user's comment about the R&D Cocktail party
VERILOG VS. VHDL (YET AGAIN): Continuing the Conflict-That-Will-Never-End,
consultants Kurt Baty and Cliff Cummings presented at SNUG the latest
proposed changes to be made to improve the next generation of Verilog.
Cliff Cummings unabashedly said: "We're proposing that Verilog pick up
the best of VHDL plus a bit more -- as if anyone could say VHDL has good
parts to it with a straight face" The ideas they put forward for
Verilog were adding: 1.) a "generate" statement, 2.) multi-dimensional
arrays, 3.) better file I/O, 4.) Re-entrant "task" statements,
5.) standardized configuration control, 6.) explict & implicit paramater
passing by name, and 7.) comma separated sensitivity lists.
"Actually, I think the room was 80 percent Verilog and 20 percent VHDL."
- Synopsys's Prasad Paranjpe (who gave the RTL-Recoding Tricks
tutorial to an audience of 283 engineers) correcting one user's
impression that the room was 70 percent Verilog and 30 percent
VHDL. At one time, Prasad was the VP of the Silicon Valley
VHDL Local User's Group.
"I hope my competition uses VHDL."
- Consultant Cliff Cummings' Internet signature of many years ago.
Cliff's new motto is: "I *still* hope my competition uses VHDL."
NEXT GENERATION SIGNOFF: Two approaches surfaced from the panel on next
generation signoff. (There was overall agreement from the panel that
designers can no longer build a gate level netlist and ship it to the
ASIC vendor.) The two new Signoff approaches in the future will be:
- customers doing physical design in-house by running floorplanning and
first pass place & route.
- or -
- RTL Sign Off (because it seems that more and more RTL tools are
emerging in terms of RTL verification/timing analysis/power analysis
/RTL floorplanning with area analysis.)
The costs involved will be: resources (engineers) to camp out at the ASIC
vendor's doorstep telling them how and where to place the logic -and/or-
$40k to $80k to spend on floorplanning tools as well as an additional $50k
to spend on Synopsys Floorplan Manager. The Cost budget for P & R tools
is an additional $250k.
Methodologies that seemed to work and held in agreement by all:
- Need to have correlation of timing analysis and logic synthesis.
- Need to floorplan/feedback into synthesis -- the floorplanned derived
wire load model including parasitics.
- Need to predict congestion & routability at the synthesis level.
- Make sure the physical and logic hierarchies are the same.
- BIST (Built In Self Test) for IP, array BIST for memories (instead of
muxes), and logic BIST for all else
Gypsies, Tramps & Thieves
-------------------------
One of the true measures of a successful conference is when it starts
getting an eco-system of parasites and hangers-ons around it. This year,
SNUG got that distinction in spades!
THE CARNIVAL IS IN TOWN! Rivals DEC, IBM, and SUN all had booths at the
SNUG Vendor Faire sporting their particular brand of workstation. But the
big winner in this marketing war was easily won by Hewlett-Packard. HP
not only had a booth at the Vendor Faire, they also had a special gypsy
trailer in the parking lot that expanded out to a full room that they
filled with HP products running demos for all three days of SNUG.
"Do you want me to send him over to the SUN booth?"
- Consultant Steve Golson upon being presented with his 13 year
old son, Jordan, by an HP staff member from the HP Workstation
Demo trailer. Jordan had just caused the HP demos to crash.
"DEC is still pushing Alpha, yet the industry-standard simulator,
Cadence's Verilog-XL, hasn't been ported to Alpha. How can DEC
pretend to be serious about EDA?"
- An anonymous user's response
TIMING IS EVERYTHING. Possibly planning for future EDA battles, Avant!
very conscientiously had their first user's group meeting on the Monday
and Tuesday directly following SNUG's Weds-Thurs-Fri. Avant! has already
publically said they intend to be a "full service EDA vendor" which
translates to "we intend to directly compete with Synopsys soon." Hmmm...
MUCH ADO ABOUT NOTHING In the weeks directly proceeding SNUG, Ambit,
ACEO, and Cadence's Alta Group all made big front page splashes in
"EE Times" claiming they were going to "challege the Synopsys monopoly
in synthesis". But I have to the give My!-But-They-Have-Big-Balls Award
to Ambit for wooing away about 15 Synopsys customers (on the Thursday
night of SNUG no less) with a great dinner and a ride in a limo to & from
the dinner, if the customers sat through a demo/ beta-customer talk. It
was fun to watch the reactions of the Synopsys employees when this piece
of news hit the grapevine! They were outraged! At a Secret Synopsys
Demos, Craig Cochran of Synopsys Marketing lamented: "We have a rule at
Synopsys that the Marketing and what you call Salesdroids can't attend
SNUG. We respect that. It's a user's conference. What annoys me is
that Ambit's marketing people violated that spirit by wisking away
customers for their sales & marketing pitch. I find their raid sleazy."
"I knew of the Ambit dinner and I must say that those guys had a lot of
guts to pick people up at the hotel like that. But on the other hand,
I think it was kind of funny and maybe it's this kind of marketing that
will let them grab a tiny, tiny, little chunk of Synopsys's business."
- Engineer Anna Ekstrandh of Nortel (Canada)
"Actually, I consider synthesis as a solved problem. I'm more
interested in design verification tools now. Do you have any?"
- Apple's David Black, at the secret Ambit/SNUG limo/dinner/demo,
after being asked by an Ambit employee: "What's your biggest
problem with synthesis today?"
Beyond the media hype, as a long time EDA industry observer, I tend to
have a wait & see attitude towards Synopsys challengers. Over the years
I've watched IBM EDA (with BooleDozer), Cadence (with Synergy), Mentor
(with AutoLogics & AutoLogics II), Intergraph/VeriBest (with warmed over
AT&T synthesis tools) all momba into the synthesis market only to be
blown away by Synopsys. What makes these 3 new contenders any different?
For expert guidance on this topic, on the flight home to Boston, I picked
up and read a book written in 1991 titled "High Tech Ventures: The Guide
For Entrepreneurial Success". It's a good book; very insightful:
"MARKETING FLAWS: Attacking Walled Cites. A classic marketing flaw
is to attack a large company's customer base with a competitive
replacement product. Rarely is this approach successful, since
customers would prefer to buy from a few suppliers that are also
the leaders." (pg.234)
"A strategy whose objective is to claim a niche from other niche
players or from newly established, aggressive start-ups is almost
certain to be fatal." (pg. 236)
It even gave indirect advice against Ambit doing the SNUG raid with:
"When attacking a walled city, a start-up shouldn't telegraph its
intentions to the inhabitants by distributing promotional coffee
cups, towels, and T-shirts." (pg. 333)
But to the book's author I must laughingly give a "Don't-Do-As-I-Do,
Do-As-I-Say...Uh...Make-That-Don't-Do-As-I-Say,-Do-As-I-Do" Award.
Why? Because that book was written by C. Gordon Bell, the Chairman of
Board of Directors of Ambit!!!
Kremlin Watching
----------------
Because I grew up on Air Force bases all over the world (my father was a
fighter pilot), I was used to hearing how, during the Cold War, U.S.
"Kremlin Watchers" would cleverly piece together all sorts of amazingly
detailed technical and political information purely from satellite photos
or by observing exactly where each Poltiburo member stood during the
Soviet's annual May Day parades in Moscow. From a Sheep Farm outside of
Boston, I'm presenting to you what I've found out about Synopsys having
just returned from the annual Synopsys Users Group (SNUG) meeting.
AART'S TECHNOLOGY LEAK #1: During the Q&A part of Aart speech, Aart said
to a user's question: "We are not selling a Formal Verification tool
yet... Yet? Did I just annouce a Synopsys product?!... Clearly we're
interested in this but, as many of you know, designs with things like
tri-states and multipliers are very hard to test by Formal Verification.
By the time we're ready to annouce a Formal Verification tool, we'll
have solutions to these problems and much more." Watch out, Chyrsalis!
AART'S TECHNOLOGY LEAK #2: In his speech, Aart displayed slides with an
8051 DesignWare part on them. Later at the Vendor Fair, I got a copy of
the 8051 MacroCell Databook. This is an unannouced Synopsys product.
In related news, it appears that the Synopsys offerings of DesignWare
parts has grown significantly within the past year.
"DOLLY" MAY BE A CLONED SHEEP, BUT "DALI" IS MORE INTERESTING: A
user installing rev. 3.5a got a very odd query from the Synopsys
installation software. Along with asking if he wanted to install
the usual VSS, Design Compiler, Behavorial Compiler, etc., he was asked
if he wanted to install something called "Protocol Compiler". Curious,
he looked up "Protocol Compiler" in the 3.5a on-line documentation. He
found over 800 pages of documentation -- everything from a User's Guide
to two complete tutorials (one in Verilog and another in VHDL) all
about "Protocol Compiler" -- otherwise known as "Dali".
It turns out that Protocol Compiler (Dali) appears to be a sort of
ESDA product that lets engineers designing chips for the Networking
or Video/Multi-Media market to intuitively capture their designs at
a graphical level and then does "static control analysis to debug the
design before lengthy RTL simulations & synthesis cycles" before
generating Verilog or VHDL for Design Compiler. It also generates
a finite state machine (in bubble diagram and source Verilog/VHDL form)
of your design's controller. Apparently, there's also some sort of
direct link between the graphical tool and simulation/synthesis.
The documentation is full of design examples involving: B-ISDN, HDLC,
X.25, ATM, SONET/SDH, JPEG, MPEG, and related technologies.
MORE TELECOM-SPECIFIC TOOLS: Also found in the documentation is a
whole set of telecom-specific tools collectively refered to as
"Telecommunications Workbenbenches". This seems to break down to
three tools: ATM Workbench, SDH Workbench, and SONET Workbench.
Apparently, Synopsys has been positioning itself for quite some time
to cash in on the lucrative Networking/Telecom & Media design markets.
RE-INVENTING A BETTER WHEEL: Because quite a few of the Chronologic
R&D team joined Synopsys after the failed attempted Chrono/ViewLogic
corporate divorce, it's widely believed that Synopsys is creating a
souped-up version of compiled Verilog that's supposed to be developed
with the benefit of knowing what worked well and didn't work well with
Chrono's VCS. Watch out, Chrono & Cadence!
IF YOU CAN'T BEAT THEM, JOIN THEM. Last year, Len Lapadula got the SNUG
1996 "Best Paper" Award for his work at Lockheed-Martin on a set of
Synopsys scripts called "Autosynthesis". Quite a few users last year
complained that although Len's paper won, none of his code was published.
Apparently, Len has joined Synopsys, Synopsys bought the rights to his
work from Lockheed-Martin and they're running an "RTL Sign-Off" synthesis
service based on "Autosynthesis". (The irony in this is that Synopsys
has banged heads with LSI Logic over LSI Logic using Design Compiler for
RTL Sign-Off and with Cadence over selling design services.)
THE SILICON ARCHITECTS PURCHASE PAID OFF YEARS AGO: One of the
controversies when Synopsys bought SiArc was whether the foundries would
buy this technology. Apparently, the gossip is that Intel has been using
the SiArc CBA technology for quite some time to build ICs, yet you won't
find a single press annoucement saying this.
ACCIDENTAL ENDORSEMENT OF SYNPLICITY: On the Friday at the end of SNUG,
the ARKOS group within Synopsys took 20 customers on a "school trip" to
go see the actual manufacturing of the ARKOS boxes. (One of the guys in
our group saw the ARKOS box for the first time and described it as "it
looked like an old 50's vintage Philips refridgerator painted blue with
a Pratt & Whitney turbofan jet-engine cooling system installed on top".)
Once we got to see the actual PCBs used to make the ARKOS box, I laughed
out loud. Why? Because I saw 5 QuickLogic FPGAs on that PCB. Synopsys
doesn't have QuickLogic synthesis libraries (because QuickLogic is such a
small FPGA vendor.) There's really only one company that has QuickLogic
synthesis libraries: Synplicity, an FPGA synthesis rival of Synopsys,
which means Synopsys had to use Synplicity to build ARKOS! :^)
WATCH OUT "MOTIVE" ... AND CADENCE, TOO! One of the worst kept secrets
in Silicon Valley is that Synopsys is developing a Static Timing Analyzer
called "PrimeTime" that will directly compete with ViewLogic's MOTIVE
product. The implicit threat that comes to Cadence (a company built on
Verilog and VHDL simulation) stems from this and the recent leak about
Synopsys working on a Formal Verification product. It clearly indicates
a future where IC Sign-Off being done *without* any simulation. (That
is, with Static Timing checking timing, and Formal Verification checking
functionality, who will need simulation then?)
QUICKTURN & SPEEDSIM VS. ARKOS & CYCLONE. Given that QuickTurn's
emulation technology is based on reprogramming FPGAs, while the far faster
non-FPGA, special custom microprocessor based ARKOS is just now hitting
the hardware emulation market, quite a few users thought that ARKOS would
be a technological death knell for QuickTurn. QuickTurn has adeptly
countered this threat by signing an OEM deal with IBM to resell IBM's
ARKOS-like emulators called "Cobalt". The schuttlebutt on this is that
although it may technologically temporarily meet the ARKOS threat, from
a business perspective it's put QuickTurn in a bind because it's hard
to make serious money when your future is based on reselling IBM boxes.
SYNOPSYS SYSTEM-ON-A-CHIP (SoC) COMING SOON? It's rumored that IBM
is in talks with Synopsys to cut some sort of deal to enable IBM to put
their in-house developed Data Networking, Telecom, and Processor-based
IP out on the market using Synopsys SoC technology. (To get a taste of
some of the technological basis of this rumored IBM/Synopsys deal just
read pgs. S312-1 through S312-25 of the Design SuperCon '97 Proceedings
in a paper entitled "Design Environment For System-On-A-Chip".)
- John Cooley
the ESNUG guy
P.S. I'm kind of curious: as a reader of ESNUG, do you like trip reports
like this that mix news, business, technology, & opinion?
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 5298 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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