ESNUG Jobs Section

  Mountain View, CA - Jasper DA seeks a CAE with at least 2 years experience in design or
  verification of digital designs with a working knowledge of the VHDL and/or Verilog design
  languages.  Candidate most have excellent communication, inter-personal skills in English,
  good analytical skills, and great common sense.

  Experience with Synopsys VCS and Vera/OpenVera, Cadence NC-Verilog, Mentor Questa/ModelSim,
  Verisity Specman "e", Novas Debussy or Verdi, is desired.

  Experience with Synopsys Magellan, Cadence IFV, Mentor 0-In static formal, hybrid formal or
  CheckerWare, IBM RuleBase, OneSpin, Averant Solidify, Real Intent Verix, Cadence Verplex
  Conformal or BlackTie, or other formal solutions, is a plus.

  Use of RedHat Linux, SunOS/Solaris Unix, Jira bug tracking, & Microsoft Office also helpful.

  Interested parties please contact Yann at yann83@jasper-da.com.  No headhunters please.

  Posted: 05/24/2007

   All Jobs Index     Next Job     Place a Job