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  Santa Clara, CA - Lightspeed seeks a senior IC design engineer.  This person will work on all
  aspects of design and implementation in a small team environment.  He/she will be responsible
  for implementing Lightspeed's AutoTest infrastructure.  Knowledge of scan methodology, and
  TetraMAX or FastScan is a plus.  Knowledge of JTAG and TAP controllers desired.  RTL coding in
  Verilog is required, VHDL is a plus.  VCS, Modelsim, Design Compiler, and PrimeTime experience
  is also required.

  Additional duties would include design of new Lightspeed IP blocks with a focus on migrating
  this IP to new process nodes or foundries -- so knowledge of Nano Enounter, Calibre, and
  VoltageStorm would be nice, but not absolutely required.

  Desirable is experience with Java/C/C++; knowledge of DSM effects and mitigation strategies.
  Candidate should be very comfortable scripting small tasks dynamically in XML or Perl.

  BSEE (MSEE preferred) with 5+ years experience in high-performance CMOS design required.

  Please contact Mike at mike27@lightspeed.com.  No recruiters please.

  Posted: 03/01/2006

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