( SNUG 99 Item 36 ) ----------------------------------------------- [3/31/99]

 HELP WANTED:  Two years ago, ECO Compiler was a Secret Project that was
 shown under NDA only to an exclusive group of Synopsys users at SNUG'97.
 Last year, ECO Compiler was announced as a product.  And since then, it's
 been having some troubles in trying to help customers respin large
 already placed & routed chips.  Someone call 911!

   "Our design process is to freeze everything for timing and to only
    isolate one small part of the chip for ECO Compiler.  We're talking
    million gate designs here; re-synthesizing for small changes is
    very costly.  It took us 3 months to get ECO Compiler to work with
    20 ECOs.  Our problems were:

        1.) Most of the tricks and effective ways to use it aren't
            documented.  It's a 20 Questions game to find this info.

        2.) We regularly got fatal errors and it took a full day to
            isolate and package the error before a Synopsys engineer
            would work on it.  Very time consuming.

        3.) Designs won't align and we're stuck with no report why!

        4.) Directives live forever.  We'd sequentially process ECOs
            and any old directive from the prior design would mess
            with the design currently being ECO-ed.

        5.) One case generated bad logic with two gate outputs tied
            together.  Synopsys has the test case.

        6.) ECOs that involve hierarchy changes won't work.  You have
            have to create dummy cells to match old & new hierarchies.

        7.) They can't handle multiple instances of sub-designs!

        8.) There's no feedback about alignment statements being accepted
            or doing anything.  Statements don't always "take" so we have
            to run eco_align 3 times to get them all.

        9.) The eco_process cannot be scripted to run successfully from
            start to finish.  It requires too much manual intervention
            and trial & error to get alignment scripts built for all of
            the special cases encountered.

       10.) Design Compiler gets indigestion doing an incremental compile
            on designs output by ECO Compiler.  We'd dont_touch everything
            but the ECO itself and DC would triple buffer non-critical
            paths (adding 200 ps) to improve a critical path by 20 ps
            making the ECO unworkable.

    We used ECO Compiler on a million gate chip.  It worked and it was
    worth it for that specific chip, but we didn't use it for any of our
    other designs.  It was too painful to use.  Another division of Unisys
    tried ECO Compiler and failed.  They bit the bullet & had to re-synth
    everything by hand.  We've met w/ Synopsys R&D a few times over this.
    They'd say that it would be easy to fix certain issues.  I wished I
    had written them down then, because a year later nothing changed.  My
    boss parlayed our ECO Compiler headaches into a PrimeTime license."

       - Ken Merryman of Unisys