( SNUG 99 Item 32 ) ----------------------------------------------- [3/31/99]

 VOTING WITH THEIR FEET ON "SYNOPSYS II"  A few years ago, Aart made a
 lot of noise about chip designers needing to "move up to higher levels of
 abstraction", which was a not-so-indirect pitch for customers to start
 using Behavioral Compiler on top of Design Compiler.  The idea was for
 Synopsys to make scads of money from BC.  The problem was that BC was, from
 a customer point of view, a real 'dog' to use.  I took the 5 day training
 class for BC and half of it was spent managing DesignWare wrappers and
 crap like that -- all to get a tool that would juggle around some adders
 and multipliers for me.  Jeez!  It was far more easier to just structure
 my Verilog/VHDL by hand to do the right thing, or, if I had time (and cash)
 to tweak a design, I'd use the easy-to-run datapath compiler from Synopsys
 called 'Module Compiler'.  (To boot, no one back in Boston wanted to risk
 using BC in their project!!)  The Big Shiney Plastic Prize one was
 supposed to get for opening the BC breakfast cereal box was BOA and BRT;
 two very nice come-ons, but not worth the hassles & headaches of BC/DW.
 So, like hiding the idiot uncle in the basement when guests visit, Synopsys
 has wisely de-emphasized BC, moved BOA/BRT into DC-Ultra, and you now see
 there are 18 Module Compiler classes for every 6 BC classes given at
 Synopsys Corporate.  At SNUG'99, for every 1 user in the BC tutorial, there
 were 5.4 users in the DC tutorial.  (This year Aart didn't mention BC.
 Inside Synopsys, he's been hailing "Physical Synthesis" as the new
 'Synopsys II'.  He's wrong.  BC was 'Synopsys II'.  "Physical Synthesis"
 is actually a 'Synopsys III'.  BC didn't fail as a tool.  It has its gaggle
 of cult devotees, faithfully using it for their designs.  BC just didn't
 conquer the mainstream chip design world as it was supposed to.)

    "A man's errors are what make him amiable."

       - Wolfgang von Goethe, German poet/philosopher, 1749 - 1832

   "BC analyzes the design based on user-specified throughput and latency
    constraints, and will automatically generate state machines, muxes,
    registers and other logic necessary to implement the desired behavior.
    The tool also analyzes register longevity to minimize unnecessary
    register usage by resource sharing, and also has the ability to map
    a storage array to different types of memories, both on-chip and
    off-chip. Control logic is automatically generated to accommodate
    user-specified memory widths and access characteristics, as well as
    automatically scheduling access to shared memories.  With increasing
    time-to-market pressures and increasing design complexity, a tool like
    BC has the potential to significantly reduce our design cycle."

       - Anon

   "Their BC people tried some of that pushing up the abstraction level
    in their talk.  Success in this area still appears to be limited to
    those companies w/ large amounts of time to devote to paving the way."

       - Anon

   "In my previous company, SGI, several designers, including myself,
    evaluated Module Compiler for 6 months, and we came to the conclusion
    that it was years ahead of any other similar tools on the market.
    This is why we opted to purchase many licenses right away.  It was
    targeted for multi-million gates design with speed equivalent to
    today's processors."

       - Jean-Didier Allegrucci of Alpine Semiconductors in ESNUG 280

   "I have been using Module Compiler since its early days (known back then
    as SiArc's DataPath Architect) to build fast arithmetic and various
    data paths structures.  Something that Design Compiler was not, in my
    experience, very good at achieving.  The tool has improved a great deal
    since then and has become an indispensable part of my design flow.  MC
    has been a great help in getting the best performance out of my
    arithmetic structures (short of hand-designing it gate-by-gate).  In
    addition, it's great for analyzing precision vs. gate-count trade-offs
    early in the design phase."

       - Adrian Jeday of SGI in ESNUG 280

    "In an ASIC design environment where time to market is top priority,
     Module Compiler is *THE* tool to use for arithmetic pipeline designs.
     It allows for very fast architectural exploration & early convergence
     on an optimal design solution.  While at SGI doing 3-D graphics chip
     design, the team's use of MC helped to cut months off our design
     cycle.  ( We're using it for the same reasons here at NVidia.)" 

        - Bob Prevett of NVidia in ESNUG 280