( SNUG 99 Item 27 ) ----------------------------------------------- [3/31/99]
GOD HELPS THOSE WHO HELP THEMSELVES: Employees from both IBM and Ford
Microelectronics presented papers on using makefile and perl scripts to
automate synthesis. The set of scripts from Ford, called SMART 2.0, was
the most automated. Basically, you just provide SMART 2.0 with a top level
set of constraints and the name of the top level module, and it figures out
the entire hierarchy of your design and does as many iterations as you want
of characterize/synthesize commands (top-down, bottom-up strategy). It
also has support for the new design budgeting feature of Synopsys. SMART
is available for free from Ford, and they will even provide phone and email
support to get you started. ("rramsay1@ford.com" or "tharring@ford.com")
Focus and Qualis created a simular tool called RUN_PROJ that's available
at www.qualis.com/cig-bin/qualis/library.pl
Cliff Cummings of Sunburst Design presented fsm_perl, a perl script that
generates Verilog code for Finite State Machines (FSMs). The designer
writes a description of a state machine in a simple format that the perl
script can read. The advantages of using the perl script are that it is
easy to maintain, it has the ability to generate Verilog in multiple FSM
styles, and it automatically generates a Synopsys synthesis script for the
FSM, that uses the Synopsys FSM tool. www.sunburst-design.com
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