( SNUG 99 Item 26 ) ----------------------------------------------- [3/31/99]
The ST Microelectronics Evaluation
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Marco Casale-Rossi of ST Microelectronics reported using Chip Architect on
parts of a 2 million gate, 0.25 um, 200 Mhz multimedia chip that had 80 to
90 utilization and more than 120 embedded RAMs. The chip was a design in
progress. It was broken up into 12 blocks and two of them were analyzed
in detail to evaluate the Chip Architect Verilog RTL-to-Placement path.
In one case, the block flow went:
Verilog RTL -> Chip Arch Placement + DC -> Cadence Silicon Ensemble Routing
In another case, the same block would go
Verilog RTL -> Design Compiler -> Cadence Silicon Ensemble Place & Routing
The results were:
Cell Routing Viol. Routing CPU Avg. Wire
RAMs Inst Gates Cdnc ChipArch Cdnc ChipArch Reduction
---- ---- ----- ---- -------- ----- -------- ---------
Blk 1 22 100K ~350K ~1800 ~900 4.3 hr 2.5 hr 7 percent
Blk 2 0 90K ~300K 0 0 19 min 38 min 12 percent
The Avg Wire Reduction was how much the Chip Architect placement reduced
the average wire length compared to using the Cadence Silicon Ensemble
placement. That is, for example in Blk 1, Cadence Silicon Ensemble found
the Chip Architect placements routed 7 percent shorter than using purely
Cadence place and route. Marco also reports that, for both blocks, he
found the post-P&R Silicon Ensemble congestion map and the Chip Architect
predicted congestion map to be virtually identical.
"Technology is part of our fundamental DNA."
- Aart De Geus, CEO of Synopsys
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