( SNUG 99 Item 25 ) ----------------------------------------------- [3/31/99]
The Panasonic Evaluation
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Keith Hirayama of Panasonic reported that they took the Verilog RTL from
two designs they already completed:
digital video camera chip (0.35 um / 3 metal / 80 Mhz)
mobile phone chip (0.25 um / 4 metal / 55 Mhz)
and compared what Chip Architect *estimated* from their source Verilog RTL
to the actual Avant! P&R final results. They were surprized to find
that Chip Architect estimates were highly accurate for long wires, even
when the wires went around intervening blocks and that 75 percent of all
nets were within +/- 10 percent of their estimates.
Keith did complain that the "RTL -> Chip Architect -> DC" run time only
averaged being 1.4 times faster than just doing the standard "RTL -> DC"
run time and wanted Synopsys to work on that. But Keith also found enough
early accuracy in Chip Architect to easily justify his customers using it
to eliminate the "Panasonic P&R <-> Customer Synthesizes" interations.
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