( SNUG 99 Item 23 ) ----------------------------------------------- [3/31/99]
THE GREAT LEAP FORWARD: Although many people understandably disagree with
what Mao Tse Tung did to the individual liberty and lives of hundreds of
millions of Chinese citizens, Mao can take credit for, in one generation,
converting a China of peasants and shopkeepers that was regularly invaded
by foreign powers into a technologically advanced China that now stands as
a nuclear superpower in her own right. My own pissing and moaning aside,
Synopsys has been very wisely focused on moving synthesis down into the
physical domain because there's only so much one can do to improve a tool
that goes from Verilog/VHDL down to gates only using front-annotated, best
guestimated wire load models. Like Mao's "Great Leap Forward", Synopsys
is re-inventing itself into a beastie focused on something called "physical
synthesis" to slay all the evil Metal-Migration, Signal Integrity, EMI,
and Wire Model dragons that lurk in the sinister depths below 0.5 micron.
1.0 0.8 0.7 0.5 0.35 0.25 0.18
----------------------------------------
Area | X X X X X X
Speed | X X X X X X X
Power | X X X X X
Metal-Migration | X X X
Signal Integrity | X X
EMI | X
The first of the New Weapons that Synopsys is carting out to deal with
these issues is a new tool called 'Chip Architect'. Chip Architect does
hierarchical floor planning, timing analysis, timing budgeting, power
planning, global routing, and congestion analysis on RTL level source
code. (And Aart says they'll be adding top-level routing soon, too.)
Rather than having their marketing spin-doctors woo us with the praises of
this new tool, Synopsys rolled out three beta customers and let them talk.
Benchmarking The New Chip Architect Placement Algorithm
-------------------------------------------------------
The first odd feature of Chip Architect that Synopsys does is to split
away placement from routing. That is, they're moving 'placement' earlier
into RTL synthesis while keeping 'routing' as a post-synthesis process.
In that vein, Synopsys claims Chip Architect uses a proprietary
breakthrough in timing driven placement algorithms. To prove this, they
brought out the following customer benchmarks.
CPU Wire Percent Clock
Name (Co or Type) Gates Time Reduct. Util. Period Process
------- ------------ ----- ---- ------ ------- ------ -------
Block A (multimedia) 750K 6 hr 17% 82% 8 ns .35u
Block B (multimedia) 250K 1.5 hr 13% 95% 8 ns .35
Block C (ST Micro) 150K 1 hr 16% 80% N/A .35
Block D (ST Micro) 20K 2 min 0% 97% 7 ns .35
The Results: "Wire Reduction" is the percentage difference between the
total wire-length after detailed routing using Synopsys Chip Architect
placement with Cadence routing as compared to using purely Cadence P&R.
(Ironically, what these wire reductions indicate is that Cadence Silicon
Ensemble did *better* routing w/ Chip Architect placed designs *than
with* Cadence placed designs!
The Details: Cadence Silicon Ensemble was used for final routing of *all*
four blocks. The pin-out and placement area was fixed by the end user and
the only variable was the use of the new Synopsys placement engine. The
netlists were placed using the timing and congestion driven placement
capability in Chip Architect. That placement was compared to results
achieved using Qplace and Silicon Ensemble from Cadence for timing driven
placement and routing. All designs routed without routing violation.
Based on customer feedback the Synopsys and Cadence placement runtimes
were comparable. The major difference was in the wire-length reported
after detailed routing.
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