( SNUG 99 Item 12 ) ----------------------------------------------- [3/31/99]
TELL THEM "COOLEY SENT YOU" Yup, I hate creating functional testbenches
as much as the next guy. Go check out www.surefirev.com. The whizkids
there who created Chrono's VCS say they have a new tool ("SureSolve")
that's supposed to take *whatever* Verilog RTL you've created 'as is' and
it *automatically* creates a set of functional test vectors for it. (It
supposedly somehow magically figures out everything from analyzing your
datapaths and control flow.) And there's also supposed to be an easy GUI
that lets you direct it to functionally test the parts that it initially
missed. If this works, please e-mail me ASAP at "jcooley@world.std.com".
I really do hate creating functional test vectors.
"I want more automatic testbench tools. I believe companies like
Surefire Verification, 0-in, and Silicon Forest Research are
addressing the real design problems of rapid verification."
- Cliff Cummings of Sunburst Design
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