( SNUG 99 Item 7 ) ----------------------------------------------- [3/31/99]
RESISTANCE IS FUTILE! <yawn> As usual, independant consultant Steve Golson
won the first place award for Best Paper at SNUG this year. (There's talk
of renaming it the 'Golson Award' because he's won 3 Best Papers so far!)
In his paper, Golson points out the problems associated with the seven
common myths surrounding wireload models plus a related graphical techique.
The 2nd place SNUG'99 paper was "FPGA Express Coding Techniques" by David
Nye of Xilinx. The 3rd place paper was "Using ACE to Simulate a Complex
PLL" by Kevin McCollough of Motorola. To see any of the SNUG'99 papers
on-line, go to www.snug-universal.org.
"Wireload models are like the weather. Many people talk about them,
but not many people *do* anything about them! This paper will explore
some of the myths and realities of wireload models:
- why wireload models are important, and why *nobody*
understands them
- why your intuition is wrong
- why you shouldn't trust your silicon vendor
- why floorplanning sometimes doesn't matter
- why having an accurate wireload model is a *bad* idea
A technique for measuring the quality of wireload models will be
described. Real-world results will be discussed. Cool graphics
will be shown. A desperate plea for future work will be given."
- the abstract to Steve Golson's 1st place SNUG'99 paper
titled "Resistance is Futile! Building Better Wireload Models"
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