( SNUG 99 Item 1 ) ----------------------------------------------- [3/31/99]
The Numbers
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Because EDA salesdroids and marketeers are known to distort/exaggerate
what other customers are doing/saying about a particular tool they're
trying to get you to buy, over the years I've found it necessary to get
the hard data myself -- whether it be the ratio of Verilog users to VHDL
users or how many customers attended a specific talk. This year, the
numbers controversy was around how many attended Aart's speech. My
count at the 30 minute mark was 367. Immediately after the speech, one of
the Synopsys people told me: "John, I had two CAE's count the room. They
counted 385." Roughly half an hour after Aart's speech was over, the
very *same* Synopsys employee told me: "John, I had two CAE's count the
room. They counted 470." I stand by my original 367.
Monday, March 29 Number Of Attendees
9:00 - 12:15 (MA1) Tutorial on Synthesis Coding Styles 239
9:00 - 12:15 (MA2) Tutorial of FPGA Compiler II 51
9:00 - 12:15 (MA4) Tutorial on Behavioral Compiler 44
9:00 - 12:15 (MA5) IP Vendor Reuse Stories & SPINE'99 69
1:30 - 3:00 (MB1) DC Wire Models & 2 Power Talks 214 + 11 standees
1:30 - 3:00 (MB2) Eagle, COSSAP, Cyclone, VERA Talks 63
1:30 - 3:00 (MB3) PrimeTime 128 + 8 standees
3:15 - 4:45 (MC1) Make, MIN/MAX Synth, Clk Gating 227 + 17 standees
3:15 - 4:45 (MC2) BFM Testing, Test Compiler 58
3:15 - 4:45 (MC3) Large FPGAs, FPGA Express 43
5:00 - 8:00 Synopsys R&D Cocktail Party Est. 600
Tuesday, March 30
9:00 - 10:15 Keynote Address (Aart's Speech) 367 or (385) or (470)
10:30 - 11:45 (TA1) Dc_shell, Verilog, VHDL, ECO Compiler 166
10:30 - 11:45 (TA2) VCS, sim/syn mismatch, LFSRS 128 + 13 standees
10:30 - 11:45 (TA3) IP Cores, IP w/ PathMill & PrimeTime 101
10:30 - 11:45 (TA4) EPIC TimeMill, Arcadia, RailMill, ACE 34
1:30 - 3:00 (TB1) Tcl, Clear Case, FSM_PERL, "Modes" 227
1:30 - 3:00 (TB2) IP Cores / Design Reuse Talks 96
3:15 - 4:45 (TC1) Make files, SMART 2.0, RUN_PROJ 161
3:15 - 4:45 (TC2) Behavioral Compiler Experiences 93
3:15 - 4:45 (TC3) Formality Experiences 83
5:00 - 5:45 SNUG'99 Wrap-Up & Best Papers Awards 216
6:00 - 8:00 Non-Synopsys EDA Vendor Fair Party over 400
Wednesday, March 31
8:00 - 11:15 (WA1) Tutorial of New Stuff in DC 99.05 178
8:00 - 11:15 (WA2) Tutorial on EPIC PathMill 25
8:00 - 11:15 (WA3) Tutorial on Design Reuse 61
8:00 - 11:15 (WA4) Tutorial on Functional Verification 33
1:00 - 4:00 (WB1) Tutorial on PrimeTime & PathMill 43
1:00 - 4:00 (WB2) Tutorial on Scan Test w/ DC Expert 31
1:00 - 4:00 (WB3) Tutorial on TimeMill & PowerMill 11
1:00 - 4:00 (WB4) Tutorial Module Compiler/BOA/BRT 135 + 7 Standees
1:00 - 4:00 (WB5) Tutorial on VCS & VERA 63
The overall user attendance for SNUG'99 was 528 customers. Compared to
the SNUG'98 numbers, 590, this is an 11 percent drop in attendance. But
that's no big surprise because SNUG normally 'partners' with OVI/VIUF
on opposite ends of a particular weekend. It just so happens that this
year, that weekend was Easter/Spring Break Weekend -- forcing the two
conferences to have 5 dead days between them. As a result, this meant
that the out-of-towners choose *either* SNUG *or* OVI/VIUF rather than
their usually going to both.
On the technical side, last year SNUG'98 had 15 tutorials and 30 user
papers. This year, SNUG'99 had 12 tutorials and 35 user papers. Last
year, SNUG'98 was 2 1/2 days; this year, SNUG'99 was 3 full days.
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