( SNUG 02 Item 16 ) -------------------------------------------- [ 5/15/02 ]
Subject: Hidden Dragon, First Encounter, Aristo IC Wizard, Soc Ensemble
A LITTLE BIT OF KNOWLEDGE: Normally, I edit ESNUG and my Trip Reports for
the engineering community with the focus on deep technical detail and user
opinion. In this section, because of the 147 Wall St. spies who'll be
reading this (see ESNUG 391 #9), I'll have to explain a basic situation
involving the physical synthesis 'block assembly' problem I've been publicly
spanking Synopsys & Cadence on. (See DAC 01 #30.) Basically I'm answering
the questions I know I'll be asked on the phone by at least 3 of these Wall
St. weenies a week after this report goes up on DeepChip. Namely: "How can
PhysOpt have 600 tape-outs with Chip Architect & Hidden Dragon not working?
How can PKS have 40 tape-outs with Integration Ensemble not working? Isn't
this a disaster for Synopsys and Cadence? Should I short the stocks?"
My quick answer: "No, those are *new* tools I'm trashing. Avanti customers
use Planet/Jupiter/Apollo & Cadence users use Silicon Ensemble/HDP to glue
together the blocks they're getting from PhysOpt or PKS. Those established
chip assembly flows work, but are slow. The Hidden Dragons and Integration
Ensembles are supposed to vastly speed up this process. They're also
supposed to enable optimal partitioning/floorplanning of a chip's blocks
before the individual blocks are fed into PhysOpt or PKS."
Sometimes a little bit of knowlege on Wall St. can be a dangerous thing.
Anyway, for the chip designers reading this, Chip Architect still sucks.
Nobody's saying all that much about Hidden Dragon, so it probably won't
be out until next month's DAC in New Orleans. Integration Ensemble or
SoC Ensemble is also Missing In Action. Maybe at DAC? Monterey (Aristo)
IC Wizard seems to be getting some attention and users are concerned that
Cadence acquiring Silicon Perspectives might crap on First Encounter's
support and development.
"Synopsys is going to take the hands off approach with Avanti for now.
The biggest conflict I see right now is between Synopsys Design
Assistant and Jupiter/Planet floorplanning. Both tools do the same
thing and Synopsys seems to advocate the use of Design Assistant (which
is bizarre since there were no presentations on it at SNUG.)"
- an anon engineer
"It's a well known that Synopsys wants to extend its realm into the
backend world. So far the only success is with PhysOpt. They gave
a demo about their "turnkey solution" -- Chip Architect + PhysOpt
+ FlexRoute. However, immediately after demo several designers
pointed out that this methodology wouldn't work for design larger
than 2 million gates. The floorplan ability of Chip Architect was
greatly questioned, and few people were using their router, let
alone the RTL2GDSII flow claimed by Synopsys. The Cisco COT team
currently uses 'First Encounter' from Silicon Perspective and most
people think the tool is very cool. Silicon Perspective had been
acquired by Cadence and let's hope that FE can still keep its
prestigious status after the acquisition."
- Andrew Cheng of Cisco
"We settled on Chip Architect, though we might find ourselves
'encouraged' to switch over to First Encounter. (They take a really
long time to make decisions here.) We looked at Monterey's IC Wizard,
but came away unconvinced that it would fit into our flow. For one
thing, we like channel-based design, rather than abutted blocks. For
another, we place strong emphasis on early floorplanning and involving
logic designers in the physical design.
While we were investigating tools, I got the feeling that most
floorplanning and partitioning software doesn't fit easily into a flow
like this. They assume you have a full netlist (i.e. logic design is
complete) before you start breaking things up. Chip Architect was the
closest fit, but even it needs a little help.
Since we use Chip Architect, are we waiting for Hidden Dragon? Not
particularly, except that it may fix some issues. Hidden Dragon's
newest features seem geared toward abutted blocks, which we don't use."
- an anon engineer
"Chip Architect what a joke; still doesn't work and where is Hidden
Dragon? The only tool that has this issue licked from the design
engineers view, and is viable, is Silicon Perspectives. Too bad that
it is now part of Cadence, we will have to see what happens in a
couple of years. Right now SPC is still an independent acting
company; which will continue to push Synopsys to get it's act
together in this area."
- Tom Tessier of t2design
"We use First Encounter for most of our design planning and prototyping
activities. I wish it had hierarchy manipulation. I wish it had more
'production-worthy' floorplanning capabilities.
We need a real partitioner, one that can take our logical design and
spit out a physical partitions that hit the sweet spot of the backend
tools. We will always trade engineering time for computer timing.
When we take a small block through the backend it takes about the same
amount of engineering time as a large block. A partitioner that could
manage constraints, too, would allow us to convert our design to a
small number of large partitions.
Haven't looked at Chip Architect yet, but seems like the tool is
now mature enough to warrant a second look. It would be intriguing
to try it out and compare to FE."
- Neel Das of Corrent Corp.
"We use Chip Architect here and it is really unstable buggy tool which
is not even a halfway descent floorplanner."
- an anon engineer
"Personally I like First Encounter, mainly because it's quick turnaround
and capacity. Chip Architect is somewhat pre-mature. I heard lots of
Hidden Dragon hype from Synopsys, but have not yet seen the demo. I
will not have too high expectations. Aristo is another floorplan tool
I will like to give a try, if I have chance, because the tool claims to
provide couple of timing vs. area suggestions."
- Miaoching Chu of Microsoft/Xbox
"There was a lot of hype about Hidden Dragon. Color me unimpressed. It
just looks like warmed over Chip Architect. Definitely a floorplanning
tool aimed at frontend designers who have never seen or done physical
design. Might be acceptable for an ASIC flow but a real SOC COT flow
requires a more powerful tool. Silicon Perspective looks like it will
fit the bill. The new Cadence PKS First Encounter (or what ever its
called these days) flow should be a real challenger to Synopsys. Add
Plato and Simplex and it should blow away Synopsys."
- an anon engineer
"I had a chance to go across the street and demo First Encounter from
Silicon Perspective a year or so ago and was very impressed. Powerful
tool that ran in next to no time. Motorola had an internal tool
(Predix) that did a lot of the same things 10 years ago but nice to
see this (and more) in a commercially available tool. The question
is, how successful will Cadence be at integrating the tool.
- Jeff Waite of Netergy Microelectronics
"Monterey's IC Wizard is a good chip level planner. It works well with
RTL, black box models, and partial gate level netlists. It can
cluster or flatten hierarchy as needed and place pins based on a quick
route, global route, and the blockages or macros inside a level of
hierarchy. Although the GUI is nice, the command line interface isn't
intuitive, and the setup is overly complex.
IC Wizard is not a good block level floorplanner, but it wasn't
intended for this. The power insertion is not DRC clean, mega cell
manual placement is difficult, and ICW lacks many options required for
a good floorplanner. Monterey has shown me a road map for the coming
releases and I can see how they are going to improve this, but the
proof is when they deliver. For now, I struggle for lack of a good
floorplanner."
- an anon engineer
"IC Wizard lets you work with a top down black box approach (and
budgetting), that allows you to perform concurrent top level design
and block design. This is a key piece of our design approach. This
approach is starting to be available in Hidden Dragon, apart from
automatic Groute based channel sizing and variable die size approach
where they have no answer. Generally speaking, we need to floorplan
bus-based SoC's before any netlist of the whole chip be available.
This is not supported efficiently by First Encounter nor Hidden Dragon
at the moment."
- an anon engineer
"Since SNUG was a primarily front end conference the oversight of
techfile correlation for the flows presented was OK as the audience
does not have to deal with that yet. It is interesting that the only
complete multi-vendor flow that was presented at both SNUG and the
Avanti Users Group was a
Planet -> Apollo/Astro -> PhysOpt -> Star -> PrimeTime
flow. This flow was presented at SNUG as a 'look how great the tools
work and PhysOpt aided getting things through STA' flow. While at the
Avanti Users Group meeting, they focused on how the flow worked but it
was a major effort to corolate the RC extraction and setup for the
floorplanner, placer, detail router and the post-layout extractor.
The Avanti users warned that you can't close timing unless you use the
same numbers for all the signoffs."
- Pallab Chatterjee of SiliconMap
"[ User Name Deleted ] told me about some of the problems they've had
with First Encounter and Sequence Sapphire. They both are good at
minimizing skew, but if you have a net with fanout, they don't want
to find the shortest path, instead giving you a scenic path. Apollo
also gives a scenic route because it wants to treat everything like a
clock and start buffering from the center of the chip. He mentioned
that Cadence is buying Sequence. He is working on a 14 mm on a side
chip 1.6 Million gate ASIC in TSMC .13 um. They are also working on
a 18 x 18 mm chip! They are using Virage for RAMs and they keep
changing timing specs with each test chip result."
- an anon engineer
"Silicon Perspective certainly has the technology edge. As far as
integration with Cadence, I am not sure if they will work it out.
Typically when Cadence buys the best technology company after 1 year,
they are probably in the 2nd or 3rd. Same thing happened when I was
a design engineer at Sun, we helped develop Pearl. The minute Cadence
bought it, PathMill and PrimeTime took over the market.
I do believe Aristo offer a good methodology for block-level, but it
will be ONLY a point tool. No comments on Magma or Chip Architect."
- an anon engineer
"Hidden Dragon and Integration Ensemble are promised for such a long
time that I don't believe in them any more. For Magma and Silicon
Perspective we made some tests but were not impressed. The race is
close and open. I don't see us using them in production for the
next 6 month."
- an anon engineer
"I have to say that SPC's FE is really impressive. We have one eval,
the whole chip ( about 1.2m logic gates) can run through within
6 hours. And definitely, SPC's (Cadence) FE is ahead in this area.
But if you only use it as for prototyping, the cost of the tool
seems too high."
- Hui Fu of Infineon
"I'm a strong believer in IC Wizard (Monterey/Aristo). I've used it in
the past and I plan to employ it here as well. Once they will
integrate the Dolphin router and timer into IC Wizard, that will be a
killer environment."
- Nir Sever of Zoran
"I have been using Monterey (Aristo) IC Wizard for about a year. Our
main use is in reading arbitrary high level Verilog, and use the tool
to partition a design across multiple large fixed sized 'containers'.
IC Wizard has the ability to graphically 'push' into the hierarchy and
re-structure it by dragging blocks across hierarchical boundaries.
It then outputs the newly restructured Verilog.
There are some limitation to the tool, like supporting only 2 regular
grids that one can snap to. This is sufficient for regular users, but
due to our unique technology we have to do some contortions to emulate
a third grid in it. It's TCL interface helps.
The version I use (2.2) already has support for automatic partitioning,
but the new version has some of Sonar's partitioning and timing
algorithms - so it should be even nicer. I just hope the price will
not go sky high. :-("
- Ze'ev Wurman of eASIC Corp.
"With all those tools did anyone say 'framework'? I didn't hear it,
but how else are customers going to manage them?"
- Jack Marshall of Tera Systems
|
|
