( SNUG 01 Item 28 ) -------------------------------------------- [ 3/28/01 ]
Subject: The Synopsys 2001 Report Card
SUCCESSFUL CHANGE: Other than that very embarrassing black eye with Chip
Architect, from a customer viewpoint, Synopsys has only messed up in
"sideshow" technologies this year. BSD Compiler's hated by all who try it.
ECO Compiler's a lost tool. Most users don't care for the new Scirocco
VHDL simulator. Formality is still getting it's ass kicked by Verplex.
Nobody's said anything positive about Eagle-i for over 2 years now. Only
one or two people in the world ever mention Protocol Compiler these days.
Behavioral Compiler has only a small cult following (even though it was
supposed to "take over the design world" when it first came out.) Gary
Smith of DataQuest sees Synopsys FPGA tools currently owning 35% market
share but he sees "the Synopsys number going down and the Synplicity number
going up" in the near future. Everybody hates the idea of designing chips
using C/C++ and even the designers at Motorola who actually used SystemC
for HW design went out of their way to write me about how much of a design
disaster SystemC is. Yup, Synopsys has it's share of hurting tools here.
But, other than Chip Arch, none of these are (or ever were) mainstream
"Big Money" tools for Synopsys. That is, SystemC is a failing experiment
right now. ECO Compiler was always a small "specialty" tool. And any EDA
vendor getting any cash out of the FPGA EDA market is a miracle in and of
itself. The mistakes Synopsys has made are mostly sideshows; not key.
On the other hand, Synopsys has made and still makes an awful lot of money
off of many key chip design technologies. Design Compiler owns the RTL
synthesis market. PrimeTime owns the Static Timing Analysis. DesignWare
owns the small IP market. Power Compiler owns its little niche. Module
Compiler owns datapath. Synopsys VCS goes roughly 55-45 with Cadence
NC-Verilog in the ~$110 million compiled Verilog market according to
DataQuest. DataQuest also reports that in '99, TetraMax and DFT Compiler
gave Synopsys 52.2% vs. Mentor's 24.0% market share in the Design For Test
business and "Mentor's marketshare should continue to shrink" according to
Gary Smith. And in one year Vera has come from behind (19% market share in
'98 to 54% market share in '99) to very dramatically overtake Verisity (78%
market share in '98 down to 33% market share in '99!)
The other news this year is Synopsys is crossbreeding its technologies.
Customers gush about Module Compiler being mixed with Design Compiler.
PrimeTime is now using EPIC technology to do crosstalk analysis. Each
DesignWare part has Vera testbenches. "I see Physical Compiler driving the
dominance of Synopsys in the DFT market," said Gary Smith of DataQuest.
VCS has its fast own VeriC/DKI C interface in addition to the PLI. The
Synopsys "0-in" tools (Ketchum and Verification Analyst) are made to
work tightly with VCS, Scirroco, Vera, and CoverMeter. Keep on mixing!
In the physical synthesis horse race, from what the customer say, Synopsys
appears to be the leading pony with its PhysOpt tool. (Yea, customers
trashed Chip Architect in this report, but Chip Arch isn't the heart of
Synopsys physical synthesis -- PhysOpt is. And it looks like Chip Arch
will be fixed or replaced by Hidden Dragon pretty damn soon, anyway.)
In the last *independently verified* tape-out count 3 months ago, Synopsys
had 65 vs. Cadence's 7 vs. Magma's 3 vs. Monterey's 0 tape-outs. From
the outside looking in, Synopsys was winning with by a 10X to 20X lead over
Cadence and Magma -- and Monterey was in trouble. For more recent but
*unverified* tape-out numbers, most engineers believe Aart's new SNUG claim
of 100 tape-outs; they have some doubts about Ray claiming 35 Cadence PKS
tape-outs, and simply don't believe Rajeev's supposed 25 Magma tape-outs.
Strategically, Synopsys has an unfair advantage over Cadence and Magma;
PhysOpt is just some new commands inside a very familiar Design Compiler
flow and GUI. (In ESNUG posts, customers have also verified that PhysOpt
works with the Cadence Silicon Ensemble, Avanti Apollo, and IBM backends
-- plus Route 66 and CTS will probably be ready within 6 months making the
backend issue moot.) Last year, 44% of Synopsys customers were designing
at or below 0.18 um. This year that number has grown to 72% of Synopsys
users! And Synopsys is taping into that. "One thing is clear: they've
got a lot of customers buying (or at least trying) this product," wrote
Paul Gerlach of Tektronix about PhysOpt.
Overall, Synopsys appears to be in a sweet position.
"Why is Aart smiling? Let’s look at the numbers. Fifteen thousand
DC current users transitioning to PhysOpt in two to three years at
an average selling price of $180,000 would mean a total market of
nearly $2.7 billion dollars even without market expansion. You can
play other more conservative scenarios and still come up with
numbers that will make Aart smile."
- Kevin Walsh, VP of Sapphire Design Automation, 12/15/00
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