( SNUG 01 Item 21 ) -------------------------------------------- [ 3/28/01 ]
Subject: Tharas Systems "Hammer" & FPGA Protyping
BIG IRON: With all this talk of C and Vera and VCS vs. NC-Verilog, it's
still interesting to see that sometimes SW just isn't fast enough.
Designers Protyping with FPGAs:
SNUG'00 ############### 31%
SNUG'01 ################### 38%
"Talked to the Tharas System guys for a while, I think they have an
interesting solution to the Simulation bottleneck. For the client
I am working with now we have found that the Hardware Modeller is
more of a bottleneck then the software simulation. If somehow the
Tharas box could be directly connected to the hardware modellers
then I think a real solution would emerge for this client."
- Tom Tessier, t2design
"Hammer (Tharas Systems - http://www.tharas.com)
-----------------------------------------------
- Hardware acceleration system
- 10K-100K cps
- Compile times: 10min/1M gate equivalent RTL
- Support for all RTL styles: clocks, latches, PLI
- All signals traceable via VCD
- Supports breakpoints
- Compatible with Verilog, Vera, VCS, Debussy
- Capacity 8M gates
Their "10K-100K cps" was on 8M gate equivalent RTL designs with
1GB memory models.
- Jerry Vauk of Sun Microsystems
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