( SNUG 01 Item 10 ) -------------------------------------------- [ 3/28/01 ]
Subject: Silicon Perspective's "First Encounter"
MORE BLOOD: And here's a user letter from Texas Instruments directly
outlining a "new PhysOpt/no-Chip Architect flow" using SPC's First
Encounter tool! (Oh, and did I forget to mention in this report that
customers weren't happy with how Chip Architect didn't work?)
"We have quite a bit of experience here at TI in the DSP group with
PhysOpt and have developed a new PhysOpt/no-Chip Architect flow.
One key aspect of the flow is that it includes First Encounter from
Silicon Perspectives. First Encounter is used for the floorplanning
and partitioning of the large designs in multiple blocks; this
partitioning includes accurate timing budgeting and pin assignment.
We evaluated Chip Architect for these tasks but found First Encounter
to be much easier to use and quite a bit faster. Physical Compiler
is used for the block-level implementation -- where block sizes are
usually in the range of 80K gates.
The key element in this flow is the timing budgeting. In our flow,
budgeting is an iterative process, starting with an initial quick
compiled netlist, and a floorplan with power grid and placement/routing
obstructions. Block-level timing budgets are derived from applying
IPO's at the top level of each hierarchical block in the design.
These initial budgets are used to drive PhysOpt from RTL-to-gates for
each of the lowest level blocks in the design.
After blocks are synthesized using initial budgets, a new netlist and
corresponding placements are generated by PhysOpt. This new netlist
consists of IPO's that were done at the top levels of each hierarchical
blocks plus the RTL-to-gates derived for each block that was
synthesized. We take this new netlist through hierarchical IPO and
pin assignment and budgeting again -- but this time the block level pin
assignments will be driven by placements that were generated by
PhysOpt.
We use the budgets generated from this refinement step to resynthesize
the blocks that do not meet timing. If after, repeated synthesis, we
don't get timing closure, it indicates that RTL changes are necessary.
We are in the process of taping out our first chip designed with this
PhysOpt/FirstEncounter flow and have started on a much larger design.
My job is to proliferate this new flow within TI."
- Surendra Mistry of Texas Instruments DSP
|
|
