( SNUG 01 Item 6 ) --------------------------------------------- [ 3/28/01 ]
Subject: Cadence NC-Verilog & NC-VHDL, Synopsys VCS & Scirroco, ModelSim
SEPARATE BUT EQUAL: Judging from the reader response, it appears that most
users now see Synopsys VCS and Cadence NC-Verilog as rough equals. And
even though at DAC'00 9 months ago Synopsys secretly demo-ed a VCS' Direct
Kernel Interface (VeriC/DKI) that allowed C object files to link directly
into VCS ("look ma!, no PLI!"), no one here mentioned that new VCS feature.
ModelSim still seems to be the slower younger brother of the VCS/NC twins
and Scirroco is still the neglected step-child in the simulation family.
"20.) What design language(s) are used in your design?"
Only Use Verilog ########################## 51%
Both VHDL & Verilog ################## 36%
Only Use VHDL ###### 13%
"I attended Synopsys' DAC presentation describing their new Direct-C
interface being built into VCS. This is long overdue: replacing the
bulky slow PLI interface with a native interface which will allow
calling C or C++ functions directly from Verilog source, allowing easy
string manipulation and file I/O.
Their "CModule" portion allows instantiation of C or C++ modules right
in the Verilog code. They have added sufficient concurrency (such as
"always @") to allow C/C++ system modeling to be used in a hardware
context. Scheduling and building the golden reference will remain a
challenge, but at least this gives us more flexibility and performance.
Synopsys claims these functions will use VCS's direct kernel interface,
be an integral part of VCS, and be delivered as a free upgrade. We
will certainly give these new features a try."
- an anon engineer ( from DAC'00 #12 of the DAC 2000 Trip Report )
"I found VCS & NC to run at about the same speed. It depends on the
design but they both are about 4x faster than XL. NC-Verilog is
harder to use and the errors and harder to spot due to the log file
file organization and length. VCS is very easy to use and suffers
only from a strange habit of sometimes having to recompile EVERYTHING
including libraries under Clearcase control.
Our management used VCS to beat down the price on more NC licenses.
Now we use NC and XL."
- David Hollinbeck of LTX Corp.
"We use Modelsim for all our simulations. We do mixed VHDL and Verilog
designs. Scirocco might interest us if Synopsys are going to
continually improve the tool. If they intend to ignore VHDL users for
another three years after releasing the new simulator, then I guess
we'll stick to Mentor!
My award for "best demo under trying circumstances" goes to Mentor. I
was given a look at Modelsim 5.5 (launched the day before DATE), they
had it running under a version of linux they don't support and because
the software had come from the U.S., it was an early cut of 5.5 (a GUI
bug was fixed between the version I saw and the release.) The result
was a demo that tried to crash everytime their apps guy tried to show
me a new feature!"
- Chris Byham of Philips Semiconductors
"For VHDL, I do not trust Scirocco. Saw VSS in a previous company and
waited for Scirocco for 2 yrs. It is not their core competency."
- an anon engineer
"We have 25 NC-Verilog licenses, 8 VCS licenses and a couple ModelSim
licenses. The designers and CAD folk prefer them in that order as
well. I have not seen too much difference between VCS and NC-Verilog,
but I would be taken outside and beaten if I told people that they
had to use ModelSim. The tool is strongly disliked because of poor
support from Mentor, a bad waveform viewer and very limited capacity,
and, did I mention it's slow?
- an anon engineer
"VCS, but we haven't benchmarked. If it ain't broke ..."
- an anon engineer
"We are strictly Verilog, so VHDL and mix VHDL/Verilog simulators are
of no interest. I did a detailed evaluation of VCS & NC on designs in
'98 and '00. In some cases NC was faster and other VCS was faster but
the delta was never greater than ~10%. As far as debug environments,
we use Novas Debussy so VCS/NC is used only as a simulator and nothing
else. With good coding standards and effective utilization of the PLI
(tf routines instead of acc) decent performance can be achieved with
either simulator. But bottom line - order of magnitude of where we
would like to be which is >100 cps.
- Jerry Vauk of Sun Microsystems
"I have benchmarked all of these, including on Suns and Linux machines.
I have found that NC-Verilog and VCS are basically equivalent. That
is, sometimes VCS is faster than NC-Verilog and sometimes NC-Verilog
is faster. Mostly it comes down to preference. Modelsim is
significantly slower than either NC-Verilog or VCS but it does seem
to have a nice interface. We don't use Modelsim though since it
benchmarked so much slower than VCS/NC-Verilog. It's cheaper, though,
so you can't really complain. Hence, we use both NC-Verilog and VCS
here since they both are about the same speed (usually the speed
differences are less than 10% on any given test case).
I have to admit I don't try to make use of any of those special
optimization switches though as that often causes me more trouble than
its worth. I have also found that on gate models that VCS will core
dump for no good reason on a particular design, sometimes when only
the testbench has changed slightly from the last time. NC-Verilog
does the same kind of thing, however, so that's why we keep both
around. If it won't run on VCS for a particular case, we use
NC-Verilog and vice-versa. So far, I have never had both core dumping
at the same time.
- Russell Petersen of Scientific Atlanta
"At my previous employer we benchmarked VCS against NC-Verilog a little
over a year ago. We found that even with the Synopsys AE present
making sure we were using VCS properly, that NC-Verilog was much (2x)
faster on our benchmark designs.
My experience with NC-Verilog is greater so I may be biased, but as a
vendor I would prefer Cadence over Synopsys anyway, so I would
definitely recommend NC-Verilog over VCS any day."
- an anon engineer
"We have both simulators in-house (many licenses) so I'm not slanting
things one way or the other. For SDF back-annotation sims, NC-Sim
heaves up and dies everytime we run it on our 3M gate ASIC. VCS
always works fine."
- an anon engineer
"The last time I benchmarked them was about two years ago. At that time
VCS was clearly ahead of NC-Verilog for our design/coding style. I
understand from some people that NC-Verilog has reached parity with
VCS. I plan to benchmark them again this month, actually, to see
whether this is true.
Even if they are even in performance, I prefer VCS to NC-Verilog for a
couple of reasons:
1. I prefer VCS' compile model. It's very simple and clean, looking
very much like a C compiler: you feed it Verilog code, and it
spits out a binary executable that you just run. One step.
It does a nice job of incremental compiles, and so forth, to make
the compile process efficient.
For NC-Verilog, on the other hand, you have to go through at least
two steps: the elaborate step, and then the compile. I never
understood why they did it that way -- hide that complexity from
the user. I don't see the gain.
2. I prefer VCS' PLI linking model. Your own PLI routines are linked
in as a library in that one compile step, with a little control
file (.tab) to tell VCS how they're used. No messing with files
in the VCS directory.
In my past experience with NC-Verilog (and especially Verilog-XL,
and even Fintronics), you had to link your PLI into some part of
the CAD vendor's tools -- and I *hate* mucking with the files in
a vendor's tools release. It just has the potential of messing
something up, and complicates support (what if you roll out
something new, and it turns out to break your whole team's
simulations...?).
That said, I'm as pragmatic as the next engineer: if NC-Verilog turns
out to give us a decided speed advantage, I'm sure we'd be asking for
a quote."
- Kris Monsen of Mobilygen Corp.
"I own a license to ModelSim and have before they got bought out by
Mentor. Often on client sites I am using either VCS or NC-Verilog for
Verilog design and ModelSim for VHDL design work. I can work with any
of them and they all have quirks. Developing scare tissue is what an
EDA Consultant does well as we are always being cut by the tools. So
you asked if I had a preference, right now for Verilog I prefer
NC-Verilog because I have used it extensively over the last year. For
VHDL, I have never preferred anything other then ModelTech. I have
done Verilog designs in ModelTech but it was much slower then
NC-Verilog at the time ~ 1 year ago."
- Tom Tessier of t2design
"We are a Modeltech house that has made extensive use of Modelsim's
integrated TCL interface to create portable chip debug tools that run
on both the simulator and on emulation or the silicon itself.
We have been asked to look at porting our TCL code to Scirocco, and
have found Scirocco as a tool to be quite resistant to the paradigm
of TCL chip debuggers. The simulator command set of Scirocco is quite
limited compared to Modelsim. For example, in Modelsim you can create
a clock in your TCL environment using the force command with the
-repeat option; the equivalent Scirocco assign command has no repeat
option. In addition Scirocco is more unstable, the Virsim interactive
enviroment is primitive when compared to Modelsim, and the restart
command strangely causes all the previous TCL procedures you have run
to be automatically re-executed (each time you restart, it re-runs
all of the commands run since starting the simulator, ad infinitum...)
It appears that the Scirocco designers have not taken the time to find
out how TCL is used by their customers in design simulation flows."
- an anon engineer
"We are a VHDL house and therefore we use ModelSim. Lately we have been
investigating running sims using Verilog gate-level netlists and SDF
files with VHDL testbenches running on MTI LNL under LINUX. We are
seeing very impressive speed improvements.
We passed on Scirocco even when Synopsys offered it to us for free."
- an anon engineer
"The Synopsys LINT checker seemed to have some promise -- especially if
they can undercut Avanti's price on ExploreRTL or whatever it's called
these days."
- an anon engineer
"I had the chance to speak with someone from Synopsys for a while. Here
is a list of some of my questions and his responses:
Q: Will VCS support the new features of Verilog 2000?
A: VCS will only support the synthesizable subset of Verilog 2000
(I have talked with others from Synopsys who say this is not true).
This means no true support for re-entrant tasks! VCS 6.0 has some
of the Verilog 2000 features, but they are undocumented because
they have not been fully tested yet.
Q: What about the future of Vera?
A: Vera will be around for a long time. There are separate development
paths for Vera and SystemC, so there is no plan to drop Vera for
SystemC. Synopsys sees SystemC as an opportunity to help develop
a standard and Vera as a product that is a source of income.
Q: Will Synopsys provide "hooks" between VCS and SystemC?
A: Yes, but only after SystemC has more time to develop. No specific
time frame was mentioned."
- Dan Joyce of Compaq Computers
"From 1993 onward, I was surprised to see that my VCS engineers
managed to to get a 2X speed-up every year -- and that's in
the software -- not from running VCS on faster workstations.
VHDL simulators have not kept up with Verilog. I don't
think VHDL will ever be as fast as Verilog because of certain
structural restrictions in VHDL. World wide, I see users
break out to 55 percent Verilog and 45 percent VHDL."
- Aart de Geus, CEO of Synopsys
What Aart may or may not realize is that 2X VCS speed-up hasn't been really
available to your average non-expert VCS user. Over the past few years, the
Synopsys VCS management has been very, VERY paranoid about the Cadence
NC-Verilog group learning about (and countering) each year's newer VCS
speed-up switches and technolgies. As a result, there have been only two
ways one could learn each year's ever newer VCS tricks. They were:
1.) If you were a Big Money Customer who regularly used lots of VCS
licenses, Synopsys would fly in their VCS specialist to spend
time training you on that year's secret new VCS tips & tricks.
2.) If you don't have that much "pull" with Synopsys as a customer,
you could hire an independent consultant like Cliff Cummings who
would teach you all the newer tricks in VCS.
But, if you were Joe Average chip designer with a limited EDA budget, you
were stuck pawing through thick (and cryptic) release notes to learn that
year's newer VCS tricks.
Contrast this with how Synopsys supports DC. They go out of their way to
repeatedly tell and tell again what each new version of DC can do. Just
look at the past SNUG and BSNUG trip reports here on the DeepChip
archives -- each report is has at *least* 20 new DC switches or useful
tricks mentioned in them. And look at how DC is handled in ESNUG;
week in and week out there's lots of detailed DC discussion going on. If
it's not some DC-Tcl script, or 12 new issues with ACS, or a DW bug -- it's
a review of Presto, or "what's this undocumented report_qor command?", or
troubles doing latch-based designs in DC. Users, FAEs, CAEs, and Synopsys
R&D are all an active part of the DC discussion in ESNUG every week. The
same thing happens with PrimeTime (where they're having a lively "monotonic
or not" lib discussion and Paul Zimmer just put out a kick ass paper on how
to handle the really ugly timing issues in PrimeTime.) VCS has no such
equivalent weekly on-going discussion happening anywhere. Sure there's
Verilog discussion on comp.lang.verilog and VCS is mentioned there sometimes;
but you're not seeing deep "here's this really useful VCS Radiant trick"
or "watch out for the Roadrunner XYZ bug in VCS 6.0 when you..." like the
weekly nitty gritty details you have for DC or PrimeTime.
The net result of this Synopsys VCS paranoia about Cadence NC-Verilog is
that your *average* VCS user doesn't know most of the hot VCS tricks. So,
he doesn't see 2X. He just sees what he gets with VCS "out of the box."
As a consequence, Synopsys now *splits* the compiled Verilog market with
Cadence when, at one time, VCS had *owned* the compiled Verilog market.
I wonder how different things would have been if the Synopsys VCS team
had openly promoted a public and intimate knowledge of each year's new
VCS tricks instead...
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