( SNUG 00 Item 23 ) -------------------------------------------- [ 4/05/00 ]
The 2000 Synopsys Report Card
-----------------------------
With the advent of hard customer data, this year's SNUG'00 conference has
yielded an amazing portrait of Synopsys and its customers. From the
customer's viewpoint, Synopsys appears to only be doing poorly in mostly
"fringe" areas. ECO Compiler is hibernating. Most customers don't seem
to care about the new Scirocco VHDL simulator announcement. Behavioral
Compiler is still very niche -- but it might bust out of that niche if
C/C++ design becomes mainstream. Protocol Compiler is practically dead.
VERA is now surprisingly used by 15 percent of Synopsys customers -- but
may die if SystemC takes off. Formality is facing some serious technical
threats from Verplex. Eaglei isn't really all that hot because it's
competing against homegrown verification. FPGA Express always seems to
be playing catch-up against Synplicity and Exemplar. And the EPIC branch
is doing a slow self-destruct sequence. Yes, this is all the bad news,
but when you look at it, they're mostly sideshows, the low revenue parts
of Synopsys that have always been low revenue.
On the flip side, Synopsys owns 91 percent of the ASIC synthesis market.
Power Compiler's hot. Module Compiler is keeping the datapath weenies in
bliss. Test Compiler and especially TetraMax are upsetting Mentor by
taking the lead in the scan insertion and ATPG markets. Static Timing
Analysis is now the way 86 percent of engineers do sign-off and, oops,
PrimeTime owns 74 percent of that market. VCS is blindingly fast, still
the strongest market leader, and, oops, Verilog accounts for 85 percent
of the North American market. Those widely used DesignWare libraries
generate mondo gravy dollars for Synopsys because 37 percent of customers
use them. More gravy because FPGA Compiler II is used by 13 percent of
customers to prototype their ASICs. And that controversial SystemC
idea opens the door to a whole new possible market of System Designers
where Synopsys is already developing new C/C++ tools to sell there.
But the biggest assets Synopsys has is the undivided attention of the high
end, big & fast chip designers. Go back and look at those stats on who
attended SNUG'00. They're 69 percent design engineers making an average
chip that's over 1 million gates, around 200 Mhz, at or below 0.18 um,
and 49 percent of them do their own Place & Route. This means Synopsys is
perfectly positioned to capitalize on the physical synthesis market. And
to my utter surprise, Synopsys appears to be winning in that strategic EDA
market with 6 (possibly 7) known, confirmed PhysOpt tape-outs of some very
serious chips from some very big customers. Compare that to Cadence's one
limp PKS tape-out that's 6 months after PhysOpt; or to Magma not having a
tape-out yet. Whoa! Chip Architect and FlexRoute are doing well, too.
Plus, Aart says he'll have Clock Tree Synthesis by DAC and a detailed
router before the end of the year. And I had originally thought that
since Cadence and Avanti dominated the backend, they'd be the obvious ones
dominating physical synthesis and Synopsys was going to be the one playing
catch-up. (Man, did I miss seeing this one coming!)
Overall, Synopsys appears to be kicking ass this year.
(Gawd! I hate having to say that. But I honestly believe it from what I'm
seeing and am therefore obligated to say it. Could some users PLEASE send
me some nice, juicy Synopsys horror stories to make me feel normal again??)
- John Cooley
the ESNUG guy
|
|
