( SNUG 00 Item 16 ) -------------------------------------------- [ 4/05/00 ]
"Actel did a presentation on the ASIC methodology for their ProASIC
family of FPGAs. They have definitely got the right idea for ASIC
prototyping with FPGAs. Their approach is to use a standard Design
Compiler ASIC flow, with no special FPGA-centric tricks or tools. With
many man-years invested in DC scripting and ASIC flow, the last thing I
want to do is learn new point tools for prototyping in FPGAs, spend many
more man-months trying to get the FPGA to route/meet timing, etc, and
have to start from scratch to make the real ASIC. Been there, done
that. I've been using this off & on for a few months, and my results
have been pretty good. The best part is that there is no FPGA-centric
wasted effort/scripting, etc. The ProASIC library looks like just
another vendor library in my DC flow. This is made possible by their
fine grain architecture and hierarchical wireload models. Instead of
having huge building blocks, they have small "tiles" with 3 inputs that
can be configured as MUXes, various gates with up to 3 inputs, or D
flipflops. It hasn't been a cakewalk since this is pretty new and the
tools/support are a work in progress, but I like it so far."
- an anon engineer
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