( SNUG 00 Item 15 ) -------------------------------------------- [ 4/05/00 ]
MOSTLY HOMEGROWN SOFTWARE TESTING: If you take a look at how the SNUG'00
attendees responded on the questions concerning the design of chips that
have a lot of related software around them:
low software chip design
with no related SW testing ############# 26%
we build a HW prototype
to test the related SW ############# 26%
we use HW/SW Co-Sim tools
to test the related SW ############ 25%
We use only SW simulation
to test the related SW ########### 23%
we use HW emulators
to test the related SW ######## 16%
Yes, it adds up to 116 percent because design teams use mixed approaches.
This is not my point here. Read on. Now take a look at these SNUG'00
user tool use stats:
Cadence Quickturn Emulation ##### 11%
IKOS Emulation #### 9%
Synopsys LMC Hardware Models ### 6%
Aptix Emulation # 2%
Denali Memory Products #### 9%
Synopsys LMC SmartModels ##### 11%
Mentor SEAMLESS HW/SW Co-Sim ## 4%
Synopsys Eaglei HW/SW Co-Sim ## 4%
Cadence SPW ### 6%
Synopsys COSSAP # 2%
You'll notice that these are relatively very low numbers. (For example,
only 8 percent of customers are using either commercial HW/SW co-sim tool,
yet right above a whopping 25 percent of customers claim to be using
HW/SW co-sim tools.) What this means is that a lot of designers are still
using the tried-and-true Verilog-with-PLI-to-run-outside-SW approach.
Basically, customers aren't buying as much as making their own. The same
holds true with prototyping:
we prototype w/ FPGAs ############### 31%
we don't prototype w/ FPGAs ################################## 69%
when you compare the 31-percent-proto-w/-FPGAs to what their commercial
equivalents are getting (for example, the 11 percent using Quickturn).
Homegrown rules, which explains the percentage of Synopsys users who also
use FPGA Compiler II:
Synopsys FPGA Express ###### 13%
Synopsys FPGA Compiler II ###### 13%
So this might mean that Synplicity and Exemplar probably aren't as big
Synopsys FPGA synthesis competitors as was originally thought -- they're
in different niches.
"The first presentation discussed the results of digital filter
implementations in FPGAs. The author explored FPGA use (as opposed
to an ASIC solution) at the direction of his management. He explored
results compiling DesignWare components into Altera FPGAs using FPGA
Compiler (fpga_shell) and FPGA Compiler II (fc2_shell), paying close
attention to design power. In summary, the results were not very good.
The speed goals were only attained by targeting less than the number of
desired bits in the filter. Also, the design power was very high due
to the SRAM lookup table architecture of FPGAs. The conclusion was
that FPGAs were too pricey ($2K) for the desired design (modems)."
- an anon engineer
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